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  • 1
    Book
    Book
    Boston : Kluwer Acad. Publ.
    UID:
    b3kat_BV024562629
    Format: IX, 193 S. , Ill.
    Edition: 5. print.
    ISBN: 0898381649
    Series Statement: The Kluwer international series in engineering and computer science
    Note: Literaturverz. S. [174] - 190
    Language: English
    Subjects: Computer Science , Engineering
    RVK:
    RVK:
    Keywords: VLSI ; Synthese ; Minimierung ; Algorithmus ; VLSI ; Optimierung
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  • 2
    UID:
    b3kat_BV040124320
    Format: 1 Online-Ressource
    ISBN: 9780387687599
    Language: English
    Keywords: Automatentheorie
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  • 3
    UID:
    b3kat_BV045187163
    Format: 1 Online-Ressource (XXI, 273 p)
    ISBN: 9781461526889
    Series Statement: The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 270
    Content: Timing research in high performance VLSI systems has advanced at a steady pace over the last few years, while tools, especially theoretical mechanisms, lag behind. Much present timing research relies heavily on timing diagrams, which, although intuitive, are inadequate for analysis of large designs with many parameters. Further, timing diagrams offer only approximations, not exact solutions, to many timing problems and provide little insight in the cases where temporal properties of a design interact intricately with the design's logical functionalities. This book presents a methodology for timing research which facilitates analy­ sis and design of circuits and systems in a unified temporal and logical domain. In the first part, we introduce an algebraic representation formalism, Timed Boolean Functions (TBF's), which integrates both logical and timing informa­ tion of digital circuits and systems into a single formalism. We also give a canonical form, TBF BDD's, for them, which can be used for efficient ma­ nipulation. In the second part, we apply Timed Boolean Functions to three problems in timing research, for which exact solutions are obtained for the first time: 1. computing the exact delays of combinational circuits and the minimum cycle times of finite state machines, 2. analysis and synthesis of wavepipelining circuits, a high speed architecture for which precise timing relations between signals are essential for correct operations, 3. verification of circuit and system performance and coverage of delay faults by testing
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461361565
    Language: English
    Keywords: Zeitverhalten ; VLSI ; Boolesche Funktion
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 4
    UID:
    b3kat_BV045187259
    Format: 1 Online-Ressource (XVII, 427 p)
    ISBN: 9781461523451
    Series Statement: The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 324
    Content: Short turnaround has become critical in the design of electronic systems. Software- programmable components such as microprocessors and digital signal processors have been used extensively in such systems since they allow rapid design revisions. However, the inherent performance limitations of software-programmable systems mean that they are inadequate for high-performance designs. Designers thus turned to gate arrays as a solution. User-programmable gate arrays (field-programmable gate arrays, FPGAs) have recently emerged and are changing the way electronic systems are designed and implemented. The growing complexity of the logic circuits that can be packed onto an FPGA chip means that it has become important to have automatic synthesis tools that implement logic functions on these architectures. Logic Synthesis for Field-Programmable Gate Arrays describes logic synthesis for both look-up table (LUT) and multiplexor-based architectures, with a balanced presentation of existing techniques together with algorithms and the system developed by the authors. Audience: A useful reference for VLSI designers, developers of computer-aided design tools, and anyone involved in or with FPGAs
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461359944
    Language: English
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 5
    UID:
    b3kat_BV045185515
    Format: 1 Online-Ressource (XXIII, 212 p)
    ISBN: 9781461539605
    Series Statement: The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 139
    Content: This book is an extension of one author's doctoral thesis on the false path problem. The work was begun with the idea of systematizing the various solutions to the false path problem that had been proposed in the literature, with a view to determining the computational expense of each versus the gain in accuracy. However, it became clear that some of the proposed approaches in the literature were wrong in that they under­ estimated the critical delay of some circuits under reasonable conditions. Further, some other approaches were vague and so of questionable accu­ racy. The focus of the research therefore shifted to establishing a theory (the viability theory) and algorithms which could be guaranteed correct, and then using this theory to justify (or not) existing approaches. Our quest was successful enough to justify presenting the full details in a book. After it was discovered that some existing approaches were wrong, it became apparent that the root of the difficulties lay in the attempts to balance computational efficiency and accuracy by separating the tempo­ ral and logical (or functional) behaviour of combinational circuits. This separation is the fruit of several unstated assumptions; first, that one can ignore the logical relationships of wires in a network when considering timing behaviour, and, second, that one can ignore timing considerations when attempting to discover the values of wires in a circuit
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461367680
    Language: English
    Keywords: VLSI ; Logischer Entwurf
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 6
    UID:
    b3kat_BV045184714
    Format: 1 Online-Ressource (XIII, 381 p)
    ISBN: 9781461561552
    Content: Synthesis of Finite State Machines: Logic Optimization is the second in a set of two monographs devoted to the synthesis of Finite State Machines (FSMs). The first volume, Synthesis of Finite State Machines: Functional Optimization, addresses functional optimization, whereas this one addresses logic optimization. The result of functional optimization is a symbolic description of an FSM which represents a sequential function chosen from a collection of permissible candidates. Logic optimization is the body of techniques for converting a symbolic description of an FSM into a hardware implementation. The mapping of a given symbolic representation into a two-valued logic implementation is called state encoding (or state assignment) and it impacts heavily area, speed, testability and power consumption of the realized circuit.
    Content: The first part of the book introduces the relevant background, presents results previously scattered in the literature on the computational complexity of encoding problems, and surveys in depth old and new approaches to encoding in logic synthesis. The second part of the book presents two main results about symbolic minimization; a new procedure to find minimal two-level symbolic covers, under face, dominance and disjunctive constraints, and a unified frame to check encodability of encoding constraints and find codes of minimum length that satisfy them. The third part of the book introduces generalized prime implicants (GPIs), which are the counterpart, in symbolic minimization of two-level logic, to prime implicants in two-valued two-level minimization. GPIs enable the design of an exact procedure for two-level symbolic minimization, based on a covering step which is complicated by the need to guarantee encodability of the final cover.
    Content: A new efficient algorithm to verify encodability of a selected cover is presented. If a cover is not encodable, it is shown how to augment it minimally until an encodable superset of GPIs is determined. To handle encodability the authors have extended the frame to satisfy encoding constraints presented in the second part. The covering problems generated in the minimization of GPIs tend to be very large. Recently large covering problems have been attacked successfully by representing the covering table with binary decision diagrams (BDD). In the fourth part of the book the authors introduce such techniques and extend them to the case of the implicit minimization of GPIs, where the encodability and augmentation steps are also performed implicitly. Synthesis of Finite State Machines: Logic Optimization will be of interest to researchers and professional engineers who work in the area of computer-aided design of integrated circuits
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461378211
    Language: English
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 7
    Book
    Book
    Boston 〈〈[u.a.]〉〉 : Kluwer
    UID:
    b3kat_BV024562628
    Format: IX, 193 S.
    ISBN: 0898381649
    Series Statement: The Kluwer international series in engineering and computer science 2 : VLSI computer architecture, and digital signal processing
    Language: Undetermined
    Subjects: Computer Science , Engineering
    RVK:
    RVK:
    Keywords: VLSI ; Synthese ; Minimierung ; Algorithmus ; VLSI ; Optimierung
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  • 8
    Online Resource
    Online Resource
    Boston, MA : Springer US
    UID:
    b3kat_BV045148668
    Format: 1 Online-Ressource (XI, 242 p)
    ISBN: 9781402080418
    Content: Regular Fabrics in Deep Sub-Micron Integrated-Circuit Design discusses new approaches to better timing-closure and manufacturability of DSM Integrated Circuits. The key idea presented is the use of regular circuit and interconnect structures such that area/delay can be predicted with high accuracy. The co-design of structures and algorithms allows great opportunities for achieving better final results, thus closing the gap between IC and CAD designers. The regularities also provide simpler and possibly better manufacturability. In this book we present not only algorithms for solving particular sub-problems but also systematic ways of organizing different algorithms in a flow to solve the design problem as a whole. A timing-driven chip design flow is developed based on the new structures and their design algorithms, which produces faster chips in a shorter time
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781402080401
    Language: English
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 9
    UID:
    b3kat_BV045148917
    Format: 1 Online-Ressource (XIX, 112 p)
    ISBN: 9781461514770
    Content: This book was motivated by the problems being faced with shrinking IC process feature sizes. It is well known that as process feature sizes shrink, a host of electrical problems like cross-talk, electromigration, self-heat, etc. are becoming important. Cross-talk is one of the major problems since it results in unpredictable design behavior. In particular, it can result in significant delay variation or signal integrity problems in a wire, depending on the state of its neighboring wires. Typical approaches to tackle the cross-talk problem attempt to fix the problem once it is created. In our approach, we ensure that cross-talk is eliminated by design. The work described in this book attempts to take an "outside-the-box" view and propose a radically different design style. This design style first imposes a fixed layout pattern (or fabric) on the integrated circuit, and then embeds the circuit being implemented into this fabric. The fabric is chosen carefully in order to eliminate the cross-talk problem being faced in modem IC processes. With our choice of fabric, cross-talk between adjacent wires on an IC is reduced by between one and two orders of magnitude. In this way, the fabric concept eliminates cross-talk up-front, and by design. We propose two separate design flows, each of which uses the fabric concept to implement logic. The first flow uses fabric-compliant standard cells as an im­ plementation vehicle. We call these cells fabric cells, and they have the same logic functionality as existing standard cells with which they are compared
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461355731
    Language: English
    Keywords: VLSI
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 10
    UID:
    b3kat_BV045187725
    Format: 1 Online-Ressource (XII, 194 p)
    ISBN: 9781461328216
    Series Statement: The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture, and Digital Signal Processing 2
    Content: The roots of the project which culminates with the writing of this book can be traced to the work on logic synthesis started in 1979 at the IBM Watson Research Center and at University of California, Berkeley. During the preliminary phases of these projects, the impor­ tance of logic minimization for the synthesis of area and performance effective circuits clearly emerged. In 1980, Richard Newton stirred our interest by pointing out new heuristic algorithms for two-level logic minimization and the potential for improving upon existing approaches. In the summer of 1981, the authors organized and participated in a seminar on logic manipulation at IBM Research. One of the goals of the seminar was to study the literature on logic minimization and to look at heuristic algorithms from a fundamental and comparative point of view. The fruits of this investigation were surprisingly abundant: it was apparent from an initial implementation of recursive logic minimiza­ tion (ESPRESSO-I) that, if we merged our new results into a two-level minimization program, an important step forward in automatic logic synthesis could result. ESPRESSO-II was born and an APL implemen­ tation was created in the summer of 1982. The results of preliminary tests on a fairly large set of industrial examples were good enough to justify the publication of our algorithms. It is hoped that the strength and speed of our minimizer warrant its Italian name, which denotes both express delivery and a specially-brewed black coffee
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461297840
    Language: English
    Keywords: VLSI ; Synthese ; Minimierung ; Algorithmus ; VLSI ; Optimierung
    URL: Volltext  (URL des Erstveröffentlichers)
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