Format:
1 Online-Ressource (142 Seiten)
ISBN:
9781627056182
,
9783031017599
Series Statement:
Synthesis Lectures on Computer Architecture #44
Content:
Intro -- Preface -- Acknowledgments -- Introduction -- The Landscape of Computation Accelerators -- GPU Hardware Basics -- A Brief History of GPUs -- Book Outline -- Programming Model -- Execution Model -- GPU Instruction Set Architectures -- NVIDIA GPU Instruction Set Architectures -- AMD Graphics Core Next Instruction Set Architecture -- The SIMT Core: Instruction and Register Data Flow -- One-Loop Approximation -- SIMT Execution Masking -- SIMT Deadlock and Stackless SIMT Architectures -- Warp Scheduling -- Two-Loop Approximation -- Three-Loop Approximation -- Operand Collector -- Instruction Replay: Handling Structural Hazards -- Research Directions on Branch Divergence -- Warp Compaction -- Intra-Warp Divergent Path Management -- Adding MIMD Capability -- Complexity-Effective Divergence Management -- Research Directions on Scalarization and Affine Execution -- Detection of Uniform or Affine Variables -- Exploiting Uniform or Affine Variables in GPU -- Research Directions on Register File Architecture -- Hierarchical Register File -- Drowsy State Register File -- Register File Virtualization -- Partitioned Register File -- RegLess -- Memory System -- First-Level Memory Structures -- Scratchpad Memory and L1 Data Cache -- L1 Texture Cache -- Unified Texture and Data Cache -- On-Chip Interconnection Network -- Memory Partition Unit -- L2 Cache -- Atomic Operations -- Memory Access Scheduler -- Research Directions for GPU Memory Systems -- Memory Access Scheduling and Interconnection Network Design -- Caching Effectiveness -- Memory Request Prioritization and Cache Bypassing -- Exploiting Inter-Warp Heterogeneity -- Coordinated Cache Bypassing -- Adaptive Cache Management -- Cache Prioritization -- Virtual Memory Page Placement -- Data Placement -- Multi-Chip-Module GPUs -- Crosscutting Research on GPU Computing Architectures
Content:
Thread Scheduling -- Research on Assignment of Threadblocks to Cores -- Research on Cycle-by-Cycle Scheduling Decisions -- Research on Scheduling Multiple Kernels -- Fine-Grain Synchronization Aware Scheduling -- Alternative Ways of Expressing Parallelism -- Support for Transactional Memory -- Kilo TM -- Warp TM and Temporal Conflict Detection -- Heterogeneous Systems -- Bibliography -- Authors' Biographies -- Blank Page
Additional Edition:
ISBN 9781627059237
Additional Edition:
ISBN 9781681733586
Additional Edition:
Erscheint auch als Druck-Ausgabe Aamodt, Tor M. General-purpose graphics processor architectures [San Rafael, California] : Morgan & Claypool Publishers, 2018 ISBN 9781681733586
Additional Edition:
ISBN 9781627059237
Language:
English
Keywords:
Electronic books
DOI:
10.1007/978-3-031-01759-9
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