Umfang:
1 Online-Ressource (123 Seiten)
Ausgabe:
Also available in print
ISBN:
1598295306
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9781598295306
Serie:
Synthesis Lectures on Digital Circuits and Systems #14
Inhalt:
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL
Inhalt:
Chapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs
Anmerkung:
Description based upon print version of record
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Foreword; ABSTRACT; xxxx; Table of Contents; Table of Figures; Calculating Maximum Clock Frequency; LEARNING OBJECTIVES; GATE PROPAGATION DELAY; Single Input/Multiple Input Delays; Propagation Delay Effects; Calculating Longest Delay Path; Example 1.1; Propagation Delays for Modern Integrated Circuits; FLIP-FLOP PROPAGATION DELAY; Asynchronous Delay; Setup and Hold Time; SEQUENTIAL SYSTEM DELAY; Pin-to-Pin Propagation Delay; Example; Clock-to-Output Delay; Example; Register-to-Register Delay; Example 1.3; Overall worst-case delay; Setup and hold adjustments; BOARD-LEVEL TIMING CALCULATION
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Datasheet compilationBoard-level maximum frequency; Example 1.5; DELAYS and TECHNOLOGY; Summary; SAMPLE EXERCISES; SAMPLE EXERCISE ANSWERS; Improving Design Performance; LEARNING OBJECTIVES; INCREASING MAXIMUM CLOCK FREQUENCY; Finite State Machine With Datapath Design; Learning Objectives; FSMD Introduction and Motivation; Fixed-point Representation; Fixed-point representation in 3D graphics; Unsigned Saturating Arithmetic and Fixed-point Numbers Fixed-point Representation; Multiplication; The blend Equation; Simple Datapaths and the blend Equation
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Registering Datapath Inputs versus Registering Datapath OutputsPipelined Computations versus Execution Unit Pipelining; Embedded Memory Usage in Finite State Machine with Datapath (FSMD) Designs; LEARNING OBJECTIVES; INTRODUCTION to EMBEDDED MEMORIES; Author Biography;
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Chapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs.
,
Also available in print.
,
Mode of access: World Wide Web.
,
System requirements: Adobe Acrobat Reader.
Weitere Ausg.:
ISBN 1598295292
Weitere Ausg.:
ISBN 9781598295290
Weitere Ausg.:
Print version Finite State Machine Datapath Design, Optimization, and Implementation
Sprache:
Englisch
Schlagwort(e):
Electronic books
DOI:
10.2200/S00087ED1V01Y200702DCS014
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