UID:
almahu_9948025886502882
Umfang:
1 online resource (735 p.)
ISBN:
1-281-07292-3
,
9786611072926
,
0-08-053040-0
Serie:
The Morgan Kaufmann Series in Computer Architecture and Design
Inhalt:
Digital arithmetic plays an important role in the design of general-purpose digital processors and of embedded systems for signal processing, graphics, and communications. In spite of a mature body of knowledge in digital arithmetic, each new generation of processors or digital systems creates new arithmetic design problems. Designers, researchers, and graduate students will find solid solutions to these problems in this comprehensive, state-of-the-art exposition of digital arithmetic.Ercegovac and Lang, two of the field's leading experts, deliver a unified treatment of digital arithme
Anmerkung:
Description based upon print version of record.
,
Front Cover; Digital Arithmetic; Copyright Page; Contents; About the Authors; Preface; Symbols and Notation; Chapter 1. Review of the Basic Number Representations and Arithmetic Algorithms; 1.1 Digital Arithmetic and Arithmetic Units; 1.2 Basic Fixed-Point Number Representation Systems; 1.3 Addition, Change of Sign, and Subtraction; 1.4 Range Extension and Arithmetic Shifts; 1.5 Basic Multiplication Algorithms; 1.6 Basic Division Algorithms; 1.7 Exercises; 1.8 Further Readings; 1.9 Bibliography; Chapter 2. Two-Operand Addition; 2.1 About Carries
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2.2 Basic Carry-Ripple Adder (CRA) and FA Implementation2.3 Reducing the Adder Delay; 2.4 Switched Carry-Ripple (Manchester) Adder; 2.5 Carry-Skip Adder; 2.6 Carry-Lookahead Adder (CLA); 2.7 Prefix Adder; 2.8 Carry-Select and Conditional-Sum Adders; 2.9 Pipelined Adders; 2.10 Variable-Time Adder; 2.11 Two's Complement and Ones' Complement Adders; 2.12 Adders with Redundant Digit Set; 2.13 Concluding Remarks; 2.14 Exercises; 2.15 Further Readings; 2.16 Bibliography; Chapter 3. Multioperand Addition; 3.1 Bit-Arrays for Unsigned and Signed Operands; 3.2 Reduction; 3.3 Sequential Implementation
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3.4 Combinational Implementation3.5 Partially Combinational Implementation; 3.6 Exercises; 3.7 Further Readings; 3.8 Bibliography; Chapter 4. Multiplication; 4.1 Sequential Multiplication with Recoding; 4.2 Combinational Multiplication with Recoding; 4.3 Partially Combinational Implementation; 4.4 Arrays of Smaller Multipliers; 4.5 Multiply-Add and Multiply-Accumulate (MAC); 4.6 Saturating Multiplier; 4.7 Truncating Multiplier; 4.8 Rectangular Multipliers; 4.9 Squarers; 4.10 Constant and Multiple-Constant Multipliers; 4.11 Concluding Remarks; 4.12 Exercises; 4.13 Further Readings
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4.14 BibliographyChapter 5. Division by Digit Recurrence; 5.1 Definition and Notation; 5.2 Algorithm and Implementation of Fractional Division; 5.3 Implementations of the Division Algorithm; 5.4 Integer Division; 5.5 Quotient-Digit Selection Function; 5.6 Concluding Remarks; 5.7 Exercises; 5.8 Further Readings; 5.9 Bibliography; Chapter 6. Square Root by Digit Recurrence; 6.1 Recurrence and Step; 6.2 Generation of Adder Input F [j]; 6.3 Overall Algorithm, Implementation, and Timing; 6.4 Combination of Division and Square Root; 6.5 Integer Square Root; 6.6 Result-Digit Selection; 6.7 Exercises
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6.8 Further Readings6.9 Bibliography; Chapter 7. Reciprocal, Division, Reciprocal Square Root, and Square Root by Iterative Approximation; 7.1 Reciprocal; 7.2 Division; 7.3 Square Root; 7.4 Example of Implementation of Division and Square Root; 7.5 Concluding Remarks; 7.6 Exercises; 7.7 Further Readings; 7.8 Bibliography; Chapter 8. Floating-Point Representation, Algorithms, and Implementations; 8.1 Floating-Point Representation; 8.2 Roundoff Modes and Error Analysis; 8.3 IEEE Standard 754; 8.4 Floating-Point Addition; 8.5 Floating-Point Multiplication
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8.6 Floating-Point Division and Square Root
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English
Weitere Ausg.:
ISBN 1-4933-0367-8
Weitere Ausg.:
ISBN 1-55860-798-6
Sprache:
Englisch
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