Format:
1 Online-Ressource (116 Seiten)
Edition:
Also available in print
ISBN:
9781608454532
Series Statement:
Synthesis Lectures on Computer Architecture #12
Content:
This lecture presents a study of the microarchitecture of contemporary microprocessors. The focus is on implementation aspects, with discussions on their implications in terms of performance, power, and cost of state-of-the-art designs. The lecture starts with an overview of the different types of microprocessors and a review of the microarchitecture of cache memories. Then, it describes the implementation of the fetch unit, where special emphasis is made on the required support for branch prediction. The next section is devoted to instruction decode with special focus on the particular support to decoding x86 instructions. The next chapter presents the allocation stage and pays special attention to the implementation of register renaming. Afterward, the issue stage is studied. Here, the logic to implement out-of-order issue for both memory and non-memory instructions is thoroughly described. The following chapter focuses on the instruction execution and describes the different functional units that can be found in contemporary microprocessors, as well as the implementation of the bypass network, which has an important impact on the performance. Finally, the lecture concludes with the commit stage, where it describes how the architectural state is updated and recovered in case of exceptions or misspeculations. This lecture is intended for an advanced course on computer architecture, suitable for graduate students or senior undergrads who want to specialize in the area of computer architecture. It is also intended for practitioners in the industry in the area of microprocessor design. The book assumes that the reader is familiar with the main concepts regarding pipelining, out-of-order execution, cache memories, and virtual memory
Content:
1. Introduction -- Classification of microarchitectures -- Pipelines/nonpipelined processors -- In-order/out-of-order processors -- Scalar/superscalar processors -- Vector processors -- Multicore processors -- Multithreaded processors -- Classification of market segments -- Overview of a processor -- Overview of the pipeline --
Content:
2. Caches -- Address translation -- Cache structure organization -- Parallel tag and data array access -- Serial tag and data array access -- Associativity considerations -- Lockup-free caches -- Implicitly addressed MSHRs -- Explicitly addressed MSHRs -- In-cache MSHRs -- Multiported caches -- True multiported cache design -- Array replication -- Virtual multiporting -- Multibanking -- Instruction caches -- Multiported vs. single ported -- Lockup free vs. blocking -- Other considerations --
Content:
3. The instruction fetch unit -- Instruction cache -- Trace cache -- Branch target buffer -- Return address stack -- Conditional branch prediction -- Static prediction -- Dynamic prediction --
Content:
4. Decode -- RISC decoding -- The x86 ISA -- Dynamic translation -- High-performance x86 decoding -- The instruction length decoder -- The dynamic translation unit --
Content:
5. Allocation -- Renaming through the reorder buffer -- Renaming through a rename buffer -- Merged register file -- Register file read -- Recovery in case of misspeculation -- Comparison of the three schemes --
Content:
6. The issue stage -- Introduction -- In-order issue logic -- Out-of-order issue logic -- Issue process when source operands are read before issue -- Issue queue allocation -- Instruction wakeup -- Instruction selection -- Entry reclamation -- Issue process when source operands are read after issue -- Read port reduction -- Other implementations for out-of-order issue -- Distributed issue queue -- Reservation stations -- Issue logic for memory operations -- Nonspeculative memory disambiguation -- Case study 1. Load ordering and store ordering on an AMD K6 processor -- Case study 2. Partial ordering on a MIPS R10000 processor -- Speculative memory disambiguation -- Case study. Alpha 21264 -- Speculative wakeup of load consumers --
Content:
7. Execute -- Functional units -- The integer arithmetic and logical unit -- Integer multiplication and division -- The address generation unit -- The branch unit -- The floating-point unit -- The SIMD unit -- Result bypassing -- Bypass in a small out-of-order machine -- Multilevel bypass for wide out-of-order machines -- Bypass for in-order machines -- Organization of functional units -- Clustering -- Clustering the bypass network -- Clustering with replicated register files -- Clustering with distributed issue queue and register files --
Content:
8. The commit stage -- Introduction -- Architectural state management -- Architectural state based on a retire register file -- Architectural state based on a merged register file -- Recovery of the speculative state -- Recovery from a branch misprediction -- Handling branch mispredictions on an ROB-based architecture with RRF -- Handling branch mispredictions on a merged register file -- Recovery from an exception -- References -- Author biographies
Note:
Description based upon print version of record
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Processor Microarchitecture An Implementation Perspective; Synthesis Lectures on Computer Architecture; ABSTRACT; Keywords; Contents; chapter 1: Introduction; 1.1 CLASSIFICATION OF MICROARCHITECTURES; 1.1.1 Pipelined/Nonpipelined Processors; 1.1.2 In-Order/Out-of-Order Processors; 1.1.3 Scalar/Superscalar Processors; 1.1.4 Vector Processors; 1.1.5 Multicore Processors; 1.1.6 Multithreaded Processors; 1.2 CLASSIFICATION OF MARKET SEGMENTS; 1.3 OVERVIEW OF A PROCESSOR; 1.3.1 Overview of the Pipeline; chapter 2: Caches; 2.1 ADDRESS TRANSLATION; 2.2 CACHE STRUCTURE ORGANIZATION
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2.2.1 Parallel Tag and Data Array Access2.2.2 Serial Tag and Data Array Access; 2.2.3 Associativity Considerations; 2.3 LOCKUP-FREE CACHES; 2.3.1 Implicitly Addressed MSHRs; 2.3.2 Explicitly Addressed MSHRs; 2.3.3 In-Cache MSHRs; 2.4 MULTIPORTED CACHES; 2.4.1 True Multiported Cache Design; 2.4.2 Array Replication; 2.4.3 Virtual Multiporting; 2.4.4 Multibanking; 2.5 INSTRUCTION CACHES; 2.5.1 Multiported vs. Single Ported; 2.5.2 Lockup Free vs. Blocking; 2.5.3 Other Considerations; chapter 3: The Instruction Fetch Unit; 3.1 INSTRUCTION CACHE; 3.1.1 Trace Cache; 3.2 BRANCH TARGET BUFFER
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3.3 RETURN ADDRESS STACK3.4 CONDITIONAL BRANCH PREDICTION; 3.4.1 Static Prediction; 3.4.2 Dynamic Prediction; chapter 4: Decode; 4.1 RISC DECODING; 4.2 THE x86 ISA; 4.3 DYNAMIC TRANSLATION; 4.4 HIGH-PERFORMANCE x86 DECODING; 4.4.1 The Instruction Length Decoder; 4.4.2 The Dynamic Translation Unit; chapter 5 Allocation; 5.1 RENAMING THROUGH THE REORDER BUFFER; 5.2 RENAMING THROUGH A RENAME BUFFER; 5.3 MERGED REGISTER FILE; 5.4 REGISTER FILE READ; 5.5 RECOVERY IN CASE OF MISSPECULATION; 5.6 COMPARISON OF THE THREE SCHEMES; chapter 6 The Issue Stage; 6.1 INTRODUCTION; 6.2 IN-ORDER ISSUE LOGIC
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6.3 OUT-OF-ORDER ISSUE LOGIC6.3.1 Issue Process when Source Operands Are Read before Issue; 6.3.1.1 Issue Queue Allocation.; 6.3.1.2 Instruction Wakeup.; 6.3.1.3 Instruction Selection.; 6.3.1.4 Entry Reclamation.; 6.3.2 Issue Process when Source Operands Are Read after Issue; 6.3.2.1 Read Port Reduction.; 6.3.3 Other Implementations for Out-of-Order Issue; 6.3.3.1 Distributed Issue Queue.; 6.3.3.2 Reservation Stations.; 6.4 ISSUE LOGIC FOR MEMORY OPERATIONS; 6.4.1 Nonspeculative Memory Disambiguation; 6.4.1.1 Case Study 1: Load Ordering and Store Ordering on an AMD K6 Processor.
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6.4.1.2 Case Study 2: Partial Ordering on a MIPS R10000 Processor.6.4.2 Speculative Memory Disambiguation; 6.4.2.1 Case Study: Alpha 21264.; 6.5 SPECULATIVE WAKEUP OF LOAD CONSUMERS; chapter 7 Execute; 7.1 FUNCTIONAL UNITS; 7.1.1 The Integer Arithmetic and Logical Unit; 7.1.2 Integer Multiplication and Division; 7.1.3 The Address Generation Unit; 7.1.4 The Branch Unit; 7.1.5 The Floating-Point Unit; 7.1.6 The SIMD Unit; 7.2 RESULT BYPASSING; 7.2.1 Bypass in a Small Out-of-Order Machine; 7.2.2 Multilevel Bypass for Wide Out-of-Order Machines; 7.2.3 Bypass for In-Order Machines
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7.2.4 Organization of Functional Units
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6. The issue stage -- Introduction -- In-order issue logic -- Out-of-order issue logic -- Issue process when source operands are read before issue -- Issue queue allocation -- Instruction wakeup -- Instruction selection -- Entry reclamation -- Issue process when source operands are read after issue -- Read port reduction -- Other implementations for out-of-order issue -- Distributed issue queue -- Reservation stations -- Issue logic for memory operations -- Nonspeculative memory disambiguation -- Case study 1. Load ordering and store ordering on an AMD K6 processor -- Case study 2. Partial ordering on a MIPS R10000 processor -- Speculative memory disambiguation -- Case study. Alpha 21264 -- Speculative wakeup of load consumers
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Also available in print.
,
System requirements: Adobe Acrobat Reader.
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Mode of access: World Wide Web.
Additional Edition:
ISBN 9781608454525
Additional Edition:
Print version Processor Microarchitecture
Language:
English
Keywords:
Electronic books
DOI:
10.2200/S00309ED1V01Y201011CAC012
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