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  • The Electrochemical Society  (68)
  • 1
    In: ECS Meeting Abstracts, The Electrochemical Society, Vol. MA2014-02, No. 40 ( 2014-08-05), p. 1959-1959
    Abstract: For the realization of a low-carbon-emission society and in terms of energy security, the grid connections of electric power systems are highly desired by applying a smart grid and high voltage DC transmission systems (HVDC). If switching devices with a break down voltage (BV) greater than 10kV are realized, it would be extremely beneficial for the reduction in size and loss of the power electronics components such as a loop power controller (LPC), a static synchronous compensator (STATCOM), and an intelligent solid state transformer (SST). Silicon carbide (SiC) is expected to be a next-generation power semiconductor material because its band gap is three times larger than that of Si. The breakdown electric field of SiC is 10 times higher than that of Si, allowing the thickness of the drift layer in SiC power devices to be 1/10 that of Si power devices. Thus, if an insulated-gate bipolar transistor (IGBT) structure of SiC is used, it will be possible to realize more than 10 kV MOS-controlled switching devices with very low on-resistance [1, 2]. We have been working on a SiC p-channel IGBT with a BV of 10 kV [4] as well as a PiN diode with a BV of 13 kV [5] . For these devices, a high-quality n ++ substrate could be used for device fabrication. However, the crystal quality of the p ++ SiC substrate for the purpose of fabricating an n-channel IGBT is currently very poor with a high micropipe density and high resistivity using it as a collector. Moreover, the channel mobility for a SiC-MOSFET is still very low compared with that of a Si-MOSFET because of its 10-times higher interface-state density (D it ). To solve these problems related to n-channel SiC-IGBTs, we employed a heavily doped epitaxial p ++ layer as a substrate and an implantation and epitaxial MOSFET (IEMOSFET) [5, 6] as a MOSFET structure, which is called a flip-type IE-IGBT. For the substrate, we attempted to fabricate a flip-type wafer utilizing a p ++ epitaxial layer as a substrate [1]. First, a 150-mm-thick n – -type drift layer was grown on the Si-face n ++ substrate after a buffer layer was formed. After the p + collector layer was grown, the p ++ substrate layer was grown to a thickness greater than 200 µm. Then, we removed the n ++ substrate, turned the substrate over, and polished the surface using the CMP process. To overcome the low channel mobility of the SiC-MOSFETs, we proposed the IEMOSFET utilizing the 4H-SiC (000-1) carbon face, which has a high channel mobility greater than 100 cm 2 /(Vs) [6]. The bottom and top of the p-well of the IE-MOSFET are formed by ion implantation and epitaxial growth, respectively. The smooth surface of the top of the p-well enables high channel mobility. A TCAD simulation was employed to optimize the design of the active area and edge termination to obtain a low forward-voltage drop (V f ) and an ultrahigh breakdown voltage. As a result, we successfully fabricated an IE-IGBT with a low V f of 5.0 V at 100 A/cm 2 with a BV greater than 16 kV [7]. At the same time, we achieved good threshold voltage (V th ) stability and a low current-density dependence on the temperature. An ultrahigh-voltage power module was assembled to evaluate the dynamic behavior of the IE-IGBT and consisted of a tungsten base plate, a DBC base with Si 3 N 4 on it, and a copper electrode. The dynamic switching performance of the combination of the ultrahigh-voltage IE-IGBT and PiN diode will be presented. [1] X. Wang, J. A. Cooper, IEEE Transactions on Electron Devices Vol. 57, No. 2, pp. 511-515, (2010) [2] S. H. Ryu, L. Cheng, S. Dhar, C. Capell, C. Jonas, J. Clayton, M. Donofrio, M. J. O’Loughlin, A. A. Burk, A. K. Agarwal, J. W. Palmour, Materials Science Forum Vols. 717-720, p. 1135 (2012) [3] S. Katakami, H. Fujisawa, K. Takenaka, H. Ishimori, S. Takasu, M. Okamoto, M. Arai, Y. Yonezawa, K. Fukuda, Materials Science Forum Vols. 740-742, p. 958 (2013) [4] D. Okamoto, Y. Tanaka, N. Matsumoto, M. Mizukami, C. Ota, K. Takao, K. Fukuda, H. Okumura, Materials Science Forum Vols. 740-742, p. 907 (2013) [5] K. Fukuda, M. Kato, J. Senzaki, K. Kojima, Appl. Phys. Lett. Vol. 84 p. 2088 (2004) [6] S. Harada, M. Kato, K. Suzuki, M. Okamoto, T. Yatsuo, K. Fukuda, K. Arai, Technical Digest of IEDM p. 903, (2006) [7] Y. Yonezawa et al., “Low V f and highly reliable 16 kV ultrahigh voltage SiC flip-type n-channel implantation and epitaxial IGBT”, in Proceedings of International Electron Devices Meeting (IEDM), 2013, pp. 6.6.1–6.6.4.
    Type of Medium: Online Resource
    ISSN: 2151-2043
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
    detail.hit.zdb_id: 2438749-6
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  • 2
    Online Resource
    Online Resource
    The Electrochemical Society ; 2009
    In:  ECS Transactions Vol. 25, No. 8 ( 2009-09-25), p. 521-524
    In: ECS Transactions, The Electrochemical Society, Vol. 25, No. 8 ( 2009-09-25), p. 521-524
    Abstract: InAs is desirable for a single nucleus in every selected growth area in micro-channel selective-area MOVPE on Si(111) substrates. In order to obtain the uniformity in the crystal shape of InGaAs micro-discs, we have devised a multi-step growth which starts from the InAs nucleation step. In this study, we have investigated the dependence of InAs nucleation on the partial pressure of an In source (PTMIn) with in situ monitoring to cover the Si surfaces by the flat InAs crystals. Since the initial nucleation of InAs is governed by the supersaturation of an In precursor on the Si surface, higher PTMIn is necessary. On the other hand, smaller PTMIn is suitable for burying the growth area by lateral growth. Therefore, we should modulate PTMIn during the InAs growth: PTMIn should be decreased as soon as the initial nucleation occurs.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2009
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  • 3
    Online Resource
    Online Resource
    The Electrochemical Society ; 2013
    In:  ECS Transactions Vol. 53, No. 3 ( 2013-05-03), p. 107-122
    In: ECS Transactions, The Electrochemical Society, Vol. 53, No. 3 ( 2013-05-03), p. 107-122
    Abstract: MOSFETs using III-V/Ge channels have been regarded as strongly important for obtaining high current drive and low supply voltage CMOS under sub 10 nm regime. However, fundamental device physics on electrical properties of III-V/Ge MOSFETs such as mobility has not been fully clarified yet. In this paper, we address key issues for enhancing channel mobility in InGaAs/Ge MOSFETs. We have confirmed in Ge p-MOSFETs with ultrathin GeO x interfacial layers formed by plasma post oxidation that the GeO x thickness can control the peak mobility in a low N s region. This fact is attributed to lower D it near E v , estimated from the S factor, in thicker GeO x . The relation between the peak mobility and the interface formation technologies is addressed. As for InGaAs nMOSFETs, we point out that the trapping of free electrons into interface states or slow states within the conduction band also significantly lowers electron mobility in InGaAs MOSFETs. As another critical factor for the electron mobility reduction, the influence of the body thickness on channel mobility is introduced. The thickness fluctuation scattering can be worse for III-V MOSFETs with lower effective mass and wider inversion-layer thickness. Thus, we have proposed MOS interface buffer channel structure, where InGaAs buffer layers sandwich InGaAs channels with higher In content. Actually, we have observed the significant mobility enhancement in the In 0 .3 Ga 0 .7 As/In 0 .7 Ga 0 .3 As/ In 0 .3 Ga 0 .7 As-OI structure over single In 0 .7 Ga 0 .3 As-OI structures.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2013
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  • 4
    Online Resource
    Online Resource
    The Electrochemical Society ; 2013
    In:  ECS Transactions Vol. 54, No. 1 ( 2013-06-28), p. 39-54
    In: ECS Transactions, The Electrochemical Society, Vol. 54, No. 1 ( 2013-06-28), p. 39-54
    Abstract: MOSFETs using III-V and Ge channels with low effective mass have been regarded as strongly important for high performance and low power CMOS under sub 10 nm regime. Key device technologies to realize the III-V/Ge MOSFETs on Si are addressed in this paper. We have recently realized HfO 2 /Al 2 O 3 gate stacks with EOT of 1 nm or less for both InGaAs and Ge, allowing us to simultaneously satisfy both thin EOT and good MOS interface properties as the common gate stacks. Record high mobility Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated by using HfO 2 /Al 2 O 3 /GeO x /Ge gate stacks. Also, self-align Ni-InGaAs is used as the metal S/D regions with low resistance, which are mandatory for shor-channel MOSFETs. We have realized 55-nm-L g InGaAs-OI MOSFETs with Ni-InGaAs S/D on Si substrates by employing direct wafer bonding between InGaAs and Si substrates with ultrathin Al 2 O 3 buried oxides. Also, by utilizing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs with superior device performance.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2013
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  • 5
    Online Resource
    Online Resource
    The Electrochemical Society ; 2013
    In:  ECS Transactions Vol. 58, No. 9 ( 2013-08-31), p. 137-148
    In: ECS Transactions, The Electrochemical Society, Vol. 58, No. 9 ( 2013-08-31), p. 137-148
    Abstract: CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/ integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for enhancing the MOSFET performance with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeO x /Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low D it and high mobility. By using these HfO 2 /Al 2 O 3 /GeO x /Ge gate stacks, Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated with high electron (690 cm 2 /Vs) and hole (550 cm 2 /Vs) mobility. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm By utilizing this channel engineering, 55 nm-L ch quantum well channel InAs-OI n-MOSFETs have been demonstrated with superior short channel effect immunity and fairly high on current.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2013
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  • 6
    Online Resource
    Online Resource
    The Electrochemical Society ; 2016
    In:  ECS Transactions Vol. 75, No. 8 ( 2016-08-18), p. 447-459
    In: ECS Transactions, The Electrochemical Society, Vol. 75, No. 8 ( 2016-08-18), p. 447-459
    Abstract: Silicon-germanium (SiGe) and germanium (Ge) have been investigated as high-mobility channel materials for high-performance metal-oxide-semiconductor field-effect transistors (MOSFETs). The intense development of heterogeneous integration of SiGe and Ge on Si has given us opportunities to extend functionalities of photonic integrated circuits based on Si photonics technologies. We have investigated strain engineering by SiGe for enhancing modulation efficiency in Si optical modulators. By using the light hole effective mass in strained SiGe, we have demonstrated the enhanced plasma dispersion effect in SiGe. In addition to low-dark-current Ge photodetectors with GeO 2 passivation, we have proposed Ge CMOS photonics for mid-infrared integrated photonics platform. We have successfully demonstrated Ge passive waveguide devices as well as carrier-injection variable optical attenuator operated at a 2-µm wavelength on Ge-on-Insulator wafer.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2016
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  • 7
    In: ECS Transactions, The Electrochemical Society, Vol. 80, No. 4 ( 2017-08-01), p. 115-124
    Type of Medium: Online Resource
    ISSN: 1938-6737 , 1938-5862
    Language: English
    Publisher: The Electrochemical Society
    Publication Date: 2017
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  • 8
    Online Resource
    Online Resource
    The Electrochemical Society ; 2018
    In:  ECS Transactions Vol. 86, No. 7 ( 2018-07-20), p. 75-86
    In: ECS Transactions, The Electrochemical Society, Vol. 86, No. 7 ( 2018-07-20), p. 75-86
    Type of Medium: Online Resource
    ISSN: 1938-6737 , 1938-5862
    Language: English
    Publisher: The Electrochemical Society
    Publication Date: 2018
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  • 9
    Online Resource
    Online Resource
    The Electrochemical Society ; 2009
    In:  ECS Transactions Vol. 16, No. 49 ( 2009-08-29), p. 221-228
    In: ECS Transactions, The Electrochemical Society, Vol. 16, No. 49 ( 2009-08-29), p. 221-228
    Abstract: Ti electrolysis by using a DC-ESR unit was performed in a CaF2-CaO-TiO2 bath, and the influence of the bath composition was discussed. Ti metal in liquid was electrodeposited though some impurity elements were contained. The cathodic current efficiency strongly depended on the bath composition, and reached about 25% in the bath where the molar ratio of CaO to TiO2 was 1.5. The consumed electric power was also affected by the bath composition so that the close relationship between the cathodic current efficiency and the electric power was seen. The influence of the bath composition was considered due to the change in the species in the bath, and Ca3Ti2O7 seemed suitable for Ti deposition.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2009
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  • 10
    Online Resource
    Online Resource
    The Electrochemical Society ; 2014
    In:  ECS Transactions Vol. 64, No. 11 ( 2014-08-07), p. 99-110
    In: ECS Transactions, The Electrochemical Society, Vol. 64, No. 11 ( 2014-08-07), p. 99-110
    Abstract: CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power logic LSIs in the future. Here, viable CMOS structures using III-V and/or Ge channels are still strongly dependent on coming progress in the device/process/integration technologies. Also, planar ultrathin body/ultrathin BOX-based multi-gate structures are preferred to suppress short channel effects and to control V th in static and/or dynamic way. In this paper, we address several key technologies to enhance the performance of III-V/Ge MOSFETs. In InGaAs/InAs n-channel MOSFETs, a parasitic resistance reduction technique is newly introduced for Ni-InGaAs metal S/D. Sub-20-nm-L ch Tri-gate InGaAs/InAs /InGaAs-OI QW MOSFETs have been demonstrated with good electrostatics. In GaSb p-MOSFETs, a metal S/D technology based on Ni is also applied to GaSb channels. The Ni-GaSb self-aligned S/D GaSb p-MOSFETs have successfully operated. In Ge MOSFETs with GeOx interfacial layers formed by plasma post oxidation, optimization of plasma post oxidation temperature and atomic Deuterium annealing were introduced. The reduction in interface roughness and interface states has effectively enhanced mobility in high N s region.
    Type of Medium: Online Resource
    ISSN: 1938-5862 , 1938-6737
    Language: Unknown
    Publisher: The Electrochemical Society
    Publication Date: 2014
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