In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 40, No. 3S ( 2001-03-01), p. 2054-
Abstract:
We have investigated design considerations for low-power single-electron transistor (SET) logic circuits. Supply-voltage scaling is introduced as a method for reducing the power consumption of SET circuits. A detailed analysis of the effects of supply-voltage scaling is given on the basis of the behavior of a complementary capacitively coupled SET inverter circuit. It has been shown that the hysteresis caused by the supply-voltage-dependent threshold voltage of a SET quickly disappears as the temperature rises, and does not ruin the desired inverting operation at a practical operation temperature. Also shown is the considerable impact of the supply-voltage scaling on reducing the power expended by leakage and short-circuit. From the results of power-delay product and delay time, it has been shown that the supply-voltage scaling should be carried out within 20% of maximum supply-voltage to maintain overall circuit performance.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.40.2054
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2001
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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