In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 44, No. 4S ( 2005-04-01), p. 2330-
Abstract:
We have investigated a Hf-based CMOSFET fabrication method that would enable the high performance and low gate leakage current that are required for the 65-nm-node CMOS devices. To suppress the gate leakage in a gate stack with an equivalent oxide thickness (EOT) of 1.2 nm, the upper layer of HfSiO film was thickened and nitrided. The nitridation improves the dielectric constant, allowing the use of a thicker HfSiO layer. The mobility was improved by lightly nitriding the bottom SiO 2 interface layer, which suppresses the interfacial trap generation. Such techniques enabled us to achieve a good EOT vs I g relationships. The I g at an EOT of 1.2 nm was reduced by three orders of magnitude as compared with that with a SiO 2 gate insulator. High mobilities, 87% of that of a SiO 2 MOSFET for an NFET and 96% for a PFET, were also obtained.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.44.2330
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2005
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
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