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  • 1
    Book
    Book
    Sequential logic testing and verification (1992)
    Boston [u.a.] : Kluwer Academic Publishers
    Details
    UID:
    gbv_019681542
    Format: XV, 214 S , graph. Darst
    ISBN: 0792391888
    Series Statement: Kluwer international series in engineering and computer science. SECS 163
    Note: Literaturverz. S. 199 - 211
    Language: English
    Subjects: Computer Science
    RVK:
    ST 190
    Keywords: Logische Schaltung ; Logischer Entwurf ; CAD
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  • 2
    Book
    Book
    Sequential logic synthesis (1992)
    Boston : Kluwer Academic Publishers
    Details
    UID:
    gbv_1608946843
    Format: XV, 225 S. , graf. Darst.
    ISBN: 079239187X
    Series Statement: Kluwer international series in engineering and computer science 162
    Note: Includes bibliographical references (p. 209-219) and index
    Language: English
    Subjects: Computer Science , Engineering
    RVK:
    ST 190
    RVK:
    ZN 5630
    Keywords: VLSI ; Entwurfsautomation ; Logische Schaltung ; Entwurfsautomation ; VLSI ; Schaltungsentwurf
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  • 3
    Online Resource
    Online Resource
    Computer-Aided Design Techniques for Low Power Sequential Logic Circuits (1997)
    Boston, MA : Springer US
    Details
    UID:
    b3kat_BV045185316
    Format: 1 Online-Ressource (XVII, 181 p)
    ISBN: 9781461563198
    Series Statement: The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 387
    Content: Rapid increases in chip complexity, increasingly faster clocks, and the proliferation of portable devices have combined to make power dissipation an important design parameter. The power consumption of a digital system determines its heat dissipation as well as battery life. For some systems, power has become the most critical design constraint. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits presents a methodology for low power design. The authors first present a survey of techniques for estimating the average power dissipation of a logic circuit. At the logic level, power dissipation is directly related to average switching activity. A symbolic simulation method that accurately computes the average switching activity in logic circuits is then described. This method is extended to handle sequential logic circuits by modeling correlation in time and by calculating the probabilities of present state lines. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits then presents a survey of methods to optimize logic circuits for low power dissipation which target reduced switching activity. A method to retime a sequential logic circuit where registers are repositioned such that the overall glitching in the circuit is minimized is also described. The authors then detail a powerful optimization method that is based on selectively precomputing the output logic values of a circuit one clock cycle before they are required, and using the precomputed value to reduce internal switching activity in the succeeding clock cycle. Presented next is a survey of methods that reduce switching activity in circuits described at the register-transfer and behavioral levels. Also described is a scheduling algorithm that reduces power dissipation by maximising the inactivity period of the modules in a given circuit. Computer-Aided Design Techniques for Low Power Sequential Logic Circuits concludes with a summary and directions for future research
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461379010
    Language: English
    Keywords: Logische Schaltung ; Verlustleistung ; Reduktion ; CAD
    DOI: 10.1007/978-1-4615-6319-8
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 4
    Online Resource
    Online Resource
    Sequential Logic Testing and Verification (1992)
    Boston, MA : Springer US
    Details
    UID:
    b3kat_BV045187844
    Format: 1 Online-Ressource (XIX, 214 p)
    ISBN: 9781461536468
    Series Statement: The Springer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 163
    Content: In order to design and build computers that achieve and sustain high performance, it is essential that reliability issues be considered care­ fully. The problem has several aspects. Certainly, considering reliability implies that an engineer must be able to analyze how design decisions affect the incidence of failure. For instance, in order design reliable inte­ gritted circuits, it is necessary to analyze how decisions regarding design rules affect the yield, i.e., the percentage of functional chips obtained by the manufacturing process. Of equal importance in producing reliable computers is the detection of failures in its Very Large Scale Integrated (VLSI) circuit components, caused by errors in the design specification, implementation, or manufacturing processes. Design verification involves the checking of the specification of a design for correctness prior to carrying out an implementation. Implementation verification ensures that the manual design or automatic synthesis process is correct, i.e., the mask-level description correctly implements the specification. Manufacture test involves the checking of the complex fabrication process for correctness, i.e., ensuring that there are no manufacturing defects in the integrated circuit. It should be noted that all the above verification mechanisms deal not only with verifying the functionality of the integrated circuit but also its performance
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461366225
    Language: English
    Keywords: Logische Schaltung ; Entwurf ; Test ; Schaltwerk ; Testen ; Logischer Entwurf ; Test
    DOI: 10.1007/978-1-4615-3646-8
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 5
    Online Resource
    Online Resource
    Sequential Logic Synthesis (1992)
    Boston, MA : Springer US
    Details
    UID:
    b3kat_BV045186225
    Format: 1 Online-Ressource (XX, 225 p)
    ISBN: 9781461536284
    Series Statement: The Kluwer International Series in Engineering and Computer Science, VLSI, Computer Architecture and Digital Signal Processing 162
    Content: 3. 2 Input Encoding Targeting Two-Level Logic . . . . . . . . 27 3. 2. 1 One-Hot Coding and Multiple-Valued Minimization 28 3. 2. 2 Input Constraints and Face Embedding 30 3. 3 Satisfying Encoding Constraints . . . . . . . 32 3. 3. 1 Definitions . . . . . . . . . . . . . . . 32 3. 3. 2 Column-Based Constraint Satisfaction 33 3. 3. 3 Row-Based Constraint Satisfaction . . 37 3. 3. 4 Constraint Satisfaction Using Dichotomies . 38 3. 3. 5 Simulated Annealing for Constraint Satisfaction 41 3. 4 Input Encoding Targeting Multilevel Logic. . 43 3. 4. 1 Kernels and Kernel Intersections . . . 44 3. 4. 2 Kernels and Multiple-Valued Variables 46 3. 4. 3 Multiple-Valued Factorization. . . . . 48 3. 4. 4 Size Estimation in Algebraic Decomposition . 53 3. 4. 5 The Encoding Step . 54 3. 5 Conclusion . . . . . . . . . 55 4 Encoding of Symbolic Outputs 57 4. 1 Heuristic Output Encoding Targeting Two-Level Logic. 59 4. 1. 1 Dominance Relations. . . . . . . . . . . . . . . . 59 4. 1. 2 Output Encoding by the Derivation of Dominance Relations . . . . . . . . . . . . . . . . . . . . . 60 . . 4. 1. 3 Heuristics to Minimize the Number of Encoding Bits . . . . . . . . . . . . 64 4. 1. 4 Disjunctive Relationships . . . . . . . . . . . 65 4. 1. 5 Summary . . . . . . . . . . . . . . . . . . 66 . . 4. 2 Exact Output Encoding Targeting Two-Level Logic. 66 4. 2. 1 Generation of Generalized Prime Implicants . 68 4. 2. 2 Selecting a Minimum Encodeable Cover . . . 68 4. 2. 3 Dominance and Disjunctive Relationships to S- isfy Constraints . . . . . . . . . . . 70 4. 2. 4 Constructing the Optimized Cover 73 4. 2. 5 Correctness of the Procedure . . 73 4. 2. 6 Multiple Symbolic Outputs . .
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781461366133
    Language: English
    Keywords: Datenverarbeitung ; Logischer Entwurf ; VLSI ; VLSI ; CAD ; Schaltwerk ; Automatentheorie
    DOI: 10.1007/978-1-4615-3628-4
    URL: Volltext  (URL des Erstveröffentlichers)
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  • 6
    Book
    Book
    Programming for the puzzled : learn to program while solving puzzles (2017)
    Cambridge, Massachusetts ; London, England : The MIT Press
    Details
    UID:
    b3kat_BV044527250
    Format: xii, 259 Seiten , Illustrationen
    ISBN: 9780262534307
    Note: Includes bibliographical references and index
    Language: English
    Subjects: Computer Science
    RVK:
    ST 301
    Keywords: Programmierung ; Programmierung ; Logikspiel
    URL: Inhaltsverzeichnis
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  • 7
    Online Resource
    Online Resource
    VLSI: Systems on a Chip : IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI’99) December 1-4, 1999, Lisboa, Portugal (2000)
    Boston, MA : Springer US
    Details
    UID:
    gbv_772887616
    Format: Online-Ressource (XVIII, 675 p) , online resource
    Edition: Springer eBook Collection. Computer Science
    ISBN: 9780387354989
    Series Statement: IFIP - The International Federation for Information Processing 34
    Content: The current trend towards the realization of complex and versatile Systems on a Chip requires the combined efforts and attention of experts in a wide range of areas including microsystems, embedded hardware/software systems, dedicated ASIC and programmable logic hardware, reconfigurable computing, wireless communications and RF issues, video and image processing, memory systems, low power design techniques, design, test and verification algorithms, modeling and simulation, logic synthesis, and interconnect analysis. Thus, the contributions presented herein address a wide range of Systems on a Chip problems. VLSI: Systems on a Chip comprises the selected proceedings of the Tenth International Conference on Very Large Scale Integration (VLSI '99), which was sponsored by the International Federation for Information Processing (IFIP) and was held in Lisbon, Portugal, in December 1999. The volume is organized around two themes, in which the following topics are addressed: VLSI Systems Design and Applications Analog Systems Design Analog Modeling and Design Image Processing Reconfigurable Computing Memory and System Design Low Power Design VLSI Design Methods and CAD Test and Verification Analog CAD and Interconnect Fundamental CAD Algorithms Verification and Simulation CAD for Physical Design High-Level Synthesis and Verification of Embedded Systems VLSI: Systems on a Chip is essential reading for researchers working on system integration, design, and CAD
    Additional Edition: ISBN 9781475710144
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781475710144
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9780792377313
    Additional Edition: Erscheint auch als Druck-Ausgabe ISBN 9781475710137
    Language: English
    DOI: 10.1007/978-0-387-35498-9
    URL: Volltext  (lizenzpflichtig)
    URL: lizenzpflichtig
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  • 8
    Online Resource
    Online Resource
    VLSI: Systems on a Chip : IFIP TC10 WG10.5 Tenth International Conference on Very Large Scale Integration (VLSI '99) December 1-4, 1999, Lisboa, Portugal (2000)
    New York, NY :Springer US :
    Details
    UID:
    almahu_9948621398402882
    Format: XXII, 678 p. , online resource.
    Edition: 1st ed. 2000.
    ISBN: 9780387354989
    Series Statement: IFIP Advances in Information and Communication Technology, 34
    Content: For over three decades now, silicon capacity has steadily been doubling every year and a half with equally staggering improvements continuously being observed in operating speeds. This increase in capacity has allowed for more complex systems to be built on a single silicon chip. Coupled with this functionality increase, speed improvements have fueled tremendous advancements in computing and have enabled new multi-media applications. Such trends, aimed at integrating higher levels of circuit functionality are tightly related to an emphasis on compactness in consumer electronic products and a widespread growth and interest in wireless communications and products. These trends are expected to persist for some time as technology and design methodologies continue to evolve and the era of Systems on a Chip has definitely come of age. While technology improvements and spiraling silicon capacity allow designers to pack more functions onto a single piece of silicon, they also highlight a pressing challenge for system designers to keep up with such amazing complexity. To handle higher operating speeds and the constraints of portability and connectivity, new circuit techniques have appeared. Intensive research and progress in EDA tools, design methodologies and techniques is required to empower designers with the ability to make efficient use of the potential offered by this increasing silicon capacity and complexity and to enable them to design, test, verify and build such systems.
    Note: Optimizing Mixer Noise Performance: A 2.4 GHz Gilbert Downconversion Mixer for W-CDMA Application -- An Analog Non-Volatile Storage System for Audio Signals with Signal Conditioning for Mobile Communication Devices -- A Design of Operational Amplifier for Sigma Delta Modulators Using 0.35um CMOS Process -- A Low Power CMOS Micromixer for GHz Wireless Applications -- High Current, Low Voltage Current Mirrors and Applications -- Nonlinearity Analysis of a Short Channel CMOS Circuit for RFIC Applications -- A Fast Parametric Model for Contact-Substrate Coupling -- A Feature Associative Processor for Image Recognition Based on A-D merged Architecture -- Massively Parallel Intelligent Pixel Implementation of a Zerotree Entropy Video Codec for Multimedia Communications -- Implementation of a Wavelet Transform Architecture for Image Processing -- Scalable Run Time Reconfigurable Architecture -- Frontier: A Fast Placement System For FPGAs -- Dynamically Reconfigurable Implementation of Control Circuits -- An IEEE Compliant Floating Point MAF -- Design and Analysis of On-Chip CPU Pipelined Caches -- Synchronous to Asynchronous Conversion - A Case Study: the Blowfish Algorithm Implementation -- Clock Distribution Strategy for IP-based Development -- An Architectural and Circuit-Level Approach to Improving the Energy Efficiency of Microprocessor Memory Structures -- Single Ended Pass-Transistor Logic - A Comparison with CMOS and CPL -- Multithreshold Voltage Technology for Low Power Bus Architecture -- Integrating Dynamic Power Management in the Design Flow -- Self-Timed Techniques for Low-Power Digital Arithmetic in GaAs VLSI -- On Defect-Level Estimation and the Clustering Effect -- FASTNR: an Efficient Fault Simulator for Linear and Nonlinear DC Circuits -- Design Error Diagnosis in Digital Circuits without Error Model -- Efficient RLC Macromodels for Digital IC Interconnect -- A Decomposition-based Symbolic Analysis Method for Analog Synthesis from Behavioral Specifications -- A Linear Programming Approach for Synthesis of Mixed-Signal Interface Elements -- RF Interface Design Using Mixed-Mode Methodology -- History-Based Dynamic Minimization During BDD Construction -- Aura II: Combining Negative Thinking and Branch-and-Bound in Unate Covering Problems -- Satisfiability-Based Functional Delay Fault Testing -- Verification of Abstracted Instruction Cache of TITAC2: A Case Study -- Speeding Up Look-up-Table Driven Logic Simulation -- Efficient Verification of Behavioral Models Using Sequential Sampling Technique -- Embedded Systems Design And Verification: Reuse Oriented Prototyping Methodologies -- A Virtual CMOS Library Approach for Fast Layout Synthesis -- RT-level Route-and-Place Design Methodology for Interconnect Optimization in DSM Regime -- Designing a Mask Programmable Matrix for Sequential Circuits -- Placement Benchmarks for 3-D VLSI -- Substrate Noise: Analysis, Models, and Optimization -- Architectural Transformations for Hierarchical Algorithmic Descriptions -- An Enhanced Static-List Scheduling Algorithm for Temporal Partitioning onto RPUs -- Object-Oriented Modeling and Co-Simulation of Embedded Systems -- Architectural Synthesis with Interconnection Cost Control -- CAE Environment for Electromechanical Microsystems -- Cost Consideration for Application Specific Microsystems Physical Design Stages - A New Approach for Microtechnological Process Design -- Moving MEMS into Mainstream Applications: The MEMSCAP Solution -- Trends in RF Simulation Algorithms -- Device Modeling and Measurement for RF Systems -- Reconfigurable Computing: Viable Applications and Trends -- Hardware Synthesis from Term Rewriting Systems -- A Synthesis Algorithm for Modular Design of Pipelined Circuits -- A Methodology and Associated CAD Tools for Support of Concurrent Design of MEMS -- SIPPs, Why Do We Need a New Standard for Interconnect Process Parameters? -- ILP-Based Board-Level Routing of Multi-Terminal Nets for Prototyping Reconfigurable Interconnect.
    In: Springer Nature eBook
    Additional Edition: Printed edition: ISBN 9781475710144
    Additional Edition: Printed edition: ISBN 9780792377313
    Additional Edition: Printed edition: ISBN 9781475710137
    Language: English
    DOI: 10.1007/978-0-387-35498-9
    URL: https://doi.org/10.1007/978-0-387-35498-9
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  • 9
    Book
    Book
    Computer-aided design techniques for low power sequential logic circuits (1997)
    Boston, Mass. [u.a.] : Kluwer Acad. Publ.
    Details
    UID:
    gbv_218812841
    Format: XIII, 181 S , graph. Darst , 25 cm
    ISBN: 0792398297
    Series Statement: Kluwer international series in engineering and computer science SECS 387
    Note: Includes bibliographical references and index , Literaturangaben
    Language: English
    Subjects: Engineering
    RVK:
    ZN 5630
    Keywords: Logische Schaltung ; Verlustleistung ; Reduktion ; CAD
    URL: Inhaltstext
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