Kooperativer Bibliotheksverbund

UID:

Format: XVIII, 258 S. : , Ill., graph. Darst.

ISBN: 978-0-12-381472-2

Note: Includes bibliographical references and index

Language: English

Subjects: Computer Science

Keywords: Parallelprozessor ; Massive Parallelität ; Programmierung

URL: http://bvbr.bib-bvb.de:8991/F?func=service&doc_library=BVB01&local_base=BVB01&doc_number=018882404&sequence=000002&line_number=0001&func_code=DB_RECORDS&service_type=MEDIA

URL: Inhaltsverzeichnis

UID:

Format: XX, 496 S. : , Ill., graph. Darst.

Edition: 2. ed.

ISBN: 978-0-12-415992-1

Language: English

Subjects: Computer Science

Keywords: Parallelprozessor ; Massive Parallelität ; Programmierung

URL: Inhaltsverzeichnis

URL: Inhaltsverzeichnis

UID:

Format: 1 online resource (xxviii, 551 pages) : , illustrations

Edition: Fourth edition.

ISBN: 0-323-98463-0 , 0-323-91231-1

Content: Programming Massively Parallel Processors: A Hands-on Approach shows both student and professional alike the basic concepts of parallel programming and GPU architecture. Various techniques for constructing parallel programs are explored in detail. Case studies demonstrate the development process, which begins with computational thinking and ends with effective and efficient parallel programs. Topics of performance, floating-point format, parallel patterns, and dynamic parallelism are covered in depth. For this new edition, the authors are updating their coverage of CUDA, including the concept of unified memory, and expanding content in areas such as threads, while still retaining its concise, intuitive, practical approach based on years of road-testing in the authors' own parallel computing courses.--

Note: Previous edition: published as by David B. Kirk, Wen-mei W. Hwu. Amsterdam: Elsevier, 2017. , Chapter 1. Introduction -- Part I: Fundamental Concepts -- Chapter 2. Heterogeneous data parallel computing -- Chapter 3. Multidimensional grids and data -- Chapter 4. Compute architecture and scheduling -- Chapter 5. Memory architecture and data locality -- Chapter 6. Performance considerations -- Part II: Parallel Patterns -- Chapter 7. Convolution: An introduction to constant memory and caching -- Chapter 8. Stencil -- Chapter 9. Parallel histogram: An introduction to atomic operations and privatization -- Chapter 10. Reduction: And minimizing divergence -- Chapter 11. Prefix sum (scan): An introduction to work efficiency in parallel algorithms -- Chapter 12. Merge: An introduction to dynamic input data identification -- Part III: Advanced Patterns and Applications -- Chapter 13. Sorting -- Chapter 14. Sparse matrix computation -- Chapter 15. Graph traversal -- Chapter 16. Deep learning -- Chapter 17. Iterative magnetic resonance imaging reconstruction -- Chapter 18. Electrostatic potential map -- Chapter 19. Parallel programming and computational thinking -- Chapter 20. Programming a heterogeneous computing cluster: An introduction to CUDA streams -- Chapter 21. CUDA dynamic parallelism -- Chapter 22. Advanced practices and future evolution -- Chapter 23. Conclusion and outlook.

Language: English

UID:

Format: 1 online resource (217 p.)

Edition: First edition.

ISBN: 0-12-800801-6

Content: Heterogeneous Systems Architecture - a new compute platform infrastructure presents a next-generation hardware platform, and associated software, that allows processors of different types to work efficiently and cooperatively in shared memory from a single source program. HSA also defines a virtual ISA for parallel routines or kernels, which is vendor and ISA independent thus enabling single source programs to execute across any HSA compliant heterogeneous processer from those used in smartphones to supercomputers. The book begins with an overview of the evolution of heterogeneous parallel processing, associated problems, and how they are overcome with HSA. Later chapters provide a deeper perspective on topics such as the runtime, memory model, queuing, context switching, the architected queuing language, simulators, and tool chains. Finally, three real world examples are presented, which provide an early demonstration of how HSA can deliver significantly higher performance thru C++ based applications. Contributing authors are HSA Foundation members who are experts from both academia and industry. Some of these distinguished authors are listed here in alphabetical order: Yeh-Ching Chung, Benedict R. Gaster, Juan Gómez-Luna, Derek Hower, Lee Howes, Shih-Hao HungThomas B. Jablin, David Kaeli,Phil Rogers, Ben Sander, I-Jui (Ray) Sung. Provides clear and concise explanations of key HSA concepts and fundamentals by expert HSA Specification contributors Explains how performance-bound programming algorithms and application types can be significantly optimized by utilizing HSA hardware and software features Presents HSA simply, clearly, and concisely without reading the detailed HSA Specification documents Demonstrates ideal mapping of processing resources from CPUs to many other heterogeneous processors that comply with HSA Specifications

Note: Description based upon print version of record. , Front Cover -- Heterogeneous System Architecture: A New Compute Platform Infrastructure -- Copyright -- Contents -- Foreword -- Preface -- About the Contributing Authors -- Chapter 1: Introduction -- Chapter 2: HSA Overview -- 2.1 A Short History of GPU Computing: The Problems That Are Solved by HSA -- 2.2 The Pillars of HSA -- 2.2.1 HSA Memory Model -- 2.2.2 HSA Queuing Model -- 2.2.3 HSAIL Virtual ISA -- 2.2.4 HSA Context Switching -- 2.3 The HSA Specifications -- 2.3.1 HSA Platform System Architecture Specification -- 2.3.2 HSA Runtime Specification -- 2.3.3 HSA Programmer's Reference Manual -a.k.a. "HSAIL Spec" -- 2.4 HSA Software -- 2.5 The HSA Foundation -- 2.6 Summary -- Chapter 3: HSAIL - Virtual Parallel ISA -- 3.1 Introduction -- 3.2 Sample Compilation Flow -- 3.3 HSAIL Execution Model -- 3.4 A Tour of the HSAIL Instruction Set -- 3.4.1 Atomic Operations -- 3.4.2 Registers -- 3.4.3 Segments -- 3.4.4 Wavefronts and Lanes -- 3.5 HSAIL Machine Models and Profiles -- 3.6 HSAIL Compilation Flow -- 3.7 HSAIL Compilation Tools -- 3.7.1 Compiler Frameworks -- 3.7.2 CL Offline Compilation (CLOC) -- 3.7.3 HSAIL Assembler/Disassembler -- 3.7.4 ISA and Machine Code Assembler/Disassembler -- 3.8 Conclusion -- Chapter 4: HSA Runtime -- 4.1 Introduction -- 4.2 The HSA Core Runtime API -- 4.2.1 Runtime Initialization and Shutdown -- 4.2.2 Runtime Notifications -- 4.2.3 System and HSA Agent Information -- 4.2.4 Signals -- 4.2.5 Queues -- 4.2.6 Architected Queuing Language -- 4.2.7 Memory -- 4.2.8 Code Objects and Executables -- 4.3 HSA Runtime Extensions -- 4.3.1 HSAIL Finalization -- 4.3.2 Images and Samplers -- 4.4 Conclusion -- References -- Chapter 5: HSA Memory Model -- 5.1 Introduction -- 5.2 HSA Memory Structure -- 5.2.1 Segments -- 5.2.2 Flat Addressing -- 5.2.3 Shared Virtual Addressing -- 5.2.4 Ownership -- 5.2.5 Image Memory. , 5.3 HSA Memory Consistency Basics -- 5.3.1 Background: Sequential Consistency -- 5.3.2 Background: Conflicts and Races -- 5.3.3 The HSA Memory Model for a Single Memory Scope -- 5.3.3.1 HSA synchronization operations -- 5.3.3.2 Transitive synchronization through different addresses -- 5.3.3.3 Finding a race -- 5.3.4 HSA Memory Model Using Memory Scopes -- 5.3.4.1 Scope motivation -- 5.3.4.2 HSA scopes -- 5.3.4.3 Using smaller scopes -- Scope inclusion -- Scope transitivity -- 5.3.5 Memory Segments -- 5.3.6 Putting It All Together: HSA Race Freedom -- 5.3.6.1 Simplified definition of HSA race freedom -- 5.3.6.2 General definition of HSA race freedom -- 5.3.7 Additional Observations and Considerations -- 5.4 Advanced Consistency in the HSA Memory Model -- 5.4.1 Relaxed Atomics -- 5.4.2 Ownership and Scope Bounding -- 5.5 Conclusions -- References -- Chapter 6: HSA Queuing Model -- 6.1 Introduction -- 6.2 User Mode Queues -- 6.3 Architected Queuing Language -- 6.3.1 Packet Types -- 6.3.2 Building Packets -- 6.4 Packet Submission and Scheduling -- 6.5 Conclusions -- References -- Chapter 7: Compiler Technology -- 7.1 Introduction -- 7.2 A Brief Introduction to C + + AMP -- 7.2.1 C++ AMP array_view -- 7.2.2 C++ AMP parallel_for_each, or Kernel Invocation -- 7.2.2.1 Lambdas or functors as kernels -- 7.2.2.2 Captured variables as kernel arguments -- 7.2.2.3 The restrict(amp) modifier -- 7.3 HSA as a Compiler Target -- 7.4 Mapping Key C++ AMP Constructs to HSA -- 7.5 C++ AMP Compilation Flow -- 7.6 Compiled C++ AMP Code -- 7.7 Compiler Support for Tiling in C++ AMP -- 7.7.1 Dividing Compute Domain -- 7.7.2 Specifying Address Space and Barriers -- 7.8 Memory Segment Annotation -- 7.9 Towards Generic C++ for HSA -- 7.10 Compiler Support for Platform Atomics -- 7.10.1 One Simple Example of Platform Atomics -- 7.11 Compiler Support for New/Delete Operators. , 7.11.1 Implementing New/Delete Operators with Platform Atomics -- 7.11.2 Promoting New/Delete Returned Address to Global Memory Segment -- 7.11.3 Improve New/Delete Operators Based on Wait API/Signal HSAIL Instruction -- 7.12 Conclusion -- References -- Chapter 8: Application Use Cases -- Platform Atomics -- 8.1 Introduction -- 8.2 Atomics in HSA -- 8.3 Task Queue System -- 8.3.1 Static Execution -- 8.3.2 Dynamic Execution -- 8.3.3 HSA Task Queue System -- 8.3.3.1 A legacy task queue system on GPU -- 8.3.3.2 A simpler, more intuitive implementation with HSA features -- 8.3.4 Evaluation -- 8.3.4.1 An experiment with synthetic input data -- 8.3.4.2 A real-world application experiment: histogram computation -- 8.4 Breadth-First Search -- 8.4.1 Legacy Implementation -- 8.4.2 HSA Implementation -- 8.4.3 Evaluation -- 8.5 Data Layout Conversion -- 8.5.1 In-place SoA-ASTA Conversion with PTTWAC Algorithm -- 8.5.2 An HSA Implementation of PTTWAC -- 8.5.3 Evaluation -- 8.6 Conclusions -- Acknowledgment -- References -- Chapter 9: HSA Simulators -- 9.1 Simulating HSA in Multi2Sim -- 9.1.1 Introduction -- 9.1.2 Multi2Sim - HSA -- 9.1.3 HSAIL Host HSA -- 9.1.3.1 Program entry -- 9.1.3.2 HSA runtime interception -- 9.1.3.3 Basic I/O support -- 9.1.4 HSA Runtime -- 9.1.5 Emulator Design -- 9.1.5.1 Emulator hierarchy -- 9.1.5.2 Memory systems -- 9.1.6 Logging and Debugging -- 9.1.7 Multi2Sim - HSA Road Map -- 9.1.8 Installation and Support -- 9.2 Emulating HSA with HSA emu -- 9.2.1 Introduction -- 9.2.2 Modeled HSA Components -- 9.2.3 Design of HSA emu -- 9.2.4 Multithreaded HSA GPU Emulator -- 9.2.4.1 HSA agent and packet processor -- 9.2.4.2 Code cache -- 9.2.4.3 HSA kernel agent and work scheduling -- 9.2.4.4 Compute unit -- 9.2.4.5 Soft- MMU and soft- TLB -- 9.2.5 Profiling, Debugging and Performance Models -- 9.3 S oft HSA Simulator. , 9.3.1 Introduction -- 9.3.2 High-Level Design -- 9.3.3 Building and Testing the Simulator -- 9.3.4 Debugging with the LLVM HSA Simulator -- References -- Index -- Back Cover.

Additional Edition: ISBN 0-12-800386-3

Language: English

Keywords: Electronic books.

URL: Click to View

UID:

Format: XIV, 318 p. , online resource.

ISBN: 9783540322726

Series Statement: Lecture Notes in Computer Science, 3793

Content: As Chairmen of HiPEAC 2005, we have the pleasure of welcoming you to the proceedings of the ?rst international conference promoted by the HiPEAC N- work of Excellence. During the last year, HiPEAC has been building its clusters of researchers in computer architecture and advanced compiler techniques for embedded and high-performance computers. Recently, the Summer School has been the seed for a fruitful collaboration of renowned international faculty and young researchers from 23 countries with fresh new ideas. Now, the conference promises to be among the premier forums for discussion and debate on these research topics. Theprestigeofasymposiumismainlydeterminedbythequalityofitstech- cal program. This ?rst programlived up to our high expectations, thanks to the largenumber of strong submissions. The ProgramCommittee received a total of 84 submissions; only 17 were selected for presentation as full-length papers and another one as an invited paper. Each paper was rigorously reviewed by three ProgramCommittee members and at least one external referee. Many reviewers spent a great amount of e?ort to provide detailed feedback. In many cases, such feedback along with constructive shepherding resulted in dramatic improvement in the quality of accepted papers. The names of the Program Committee m- bers and the referees are listed in the proceedings. The net result of this team e?ort is that the symposium proceedings include outstanding contributions by authors from nine countries in three continents. In addition to paper presentations, this ?rst HiPEAC conference featured two keynotes delivered by prominent researchers from industry and academia.

Note: Invited Program -- Keynote 1: Using EEMBC Benchmarks to Understand Processor Behavior in Embedded Applications -- Keynote 2: The Chip-Multiprocessing Paradigm Shift: Opportunities and Challenges -- Software Defined Radio – A High Performance Embedded Challenge -- I Analysis and Evaluation Techniques -- A Practical Method for Quickly Evaluating Program Optimizations -- Efficient Sampling Startup for Sampled Processor Simulation -- Enhancing Network Processor Simulation Speed with Statistical Input Sampling -- II Novel Memory and Interconnect Architectures -- Power Aware External Bus Arbitration for System-on-a-Chip Embedded Systems -- Beyond Basic Region Caching: Specializing Cache Structures for High Performance and Energy Conservation -- Streaming Sparse Matrix Compression/Decompression -- XAMM: A High-Performance Automatic Memory Management System with Memory-Constrained Designs -- III Security Architecture -- Memory-Centric Security Architecture -- A Novel Batch Rekeying Processor Architecture for Secure Multicast Key Management -- Arc3D: A 3D Obfuscation Architecture -- IV Novel Compiler and Runtime Techniques -- Dynamic Code Region (DCR) Based Program Phase Tracking and Prediction for Dynamic Optimizations -- Induction Variable Analysis with Delayed Abstractions -- Garbage Collection Hints -- V DomainSpecificArchitectures -- Exploiting a Computation Reuse Cache to Reduce Energy in Network Processors -- Dynamic Evolution of Congestion Trees: Analysis and Impact on Switch Architecture -- A Single (Unified) Shader GPU Microarchitecture for Embedded Systems -- A Low-Power DSP-Enhanced 32-Bit EISC Processor.

In: Springer eBooks

Additional Edition: Printed edition: ISBN 9783540303176

Language: English

Subjects: Computer Science

Keywords: Konferenzschrift

DOI: 10.1007/11587514

URL: http://dx.doi.org/10.1007/11587514

URL: Volltext  (lizenzpflichtig)

URL: Volltext  (lizenzpflichtig)

URL: Cover

UID:

Format: 1 Online-Ressource (xvi, 541 p., [16] p. of plates)

Edition: Jade ed

ISBN: 9780123859631 , 0123859638 , 9780123859648 , 0123859646 , 9781283288200 , 1283288206

Series Statement: Applications of GPU computing

Note: This is the second volume of Morgan Kaufmann's GPU Computing Gems, offering an all-new set of insights, ideas, and practical "hands-on" skills from researchers and developers worldwide. Each chapter gives you a window into the work being performed across a variety of application domains, and the opportunity to witness the impact of parallel GPU computing on the efficiency of scientific research. GPU Computing Gems: Jade Edition showcases the latest research solutions with GPGPU and CUDA, including: Improving memory access patterns for cellular automata using CUDA Large-scale gas turbine simulations on GPU clusters Identifying and mitigating credit risk using large-scale economic capital simulations GPU-powered MATLAB acceleration with Jacket Biologically-inspired machine vision An efficient CUDA algorithm for the maximum network flow problem 30 more chapters of innovative GPU computing ideas, written to be accessible to researchers from any industry GPU Computing Gems: Jade Edition contains 100% new material covering a variety of application domains: algorithms and data structures, engineering, interactive physics for games, computational finance, and programming tools. This second volume of GPU Computing Gems offers 100% new material of interest across industry, including finance, medicine, imaging, engineering, gaming, environmental science, green computing, and more Covers new tools and frameworks for productive GPU computing application development and offers immediate benefit to researchers developing improved programming environments for GPUs Even more hands-on, proven techniques demonstrating how general purpose GPU computing is changing scientific research Distills the best practices of the community of CUDA programmers; each chapter provides insights and ideas as well as 'hands on' skills applicable to a variety of fields , "Since the introduction of CUDA in 2007, more than 100 million computers with CUDA capable GPUs have been shipped to end users. GPU computing application developers can now expect their application to have a mass market. With the introduction of OpenCL in 2010, researchers can now expect to develop GPU applications that can run on hardware from multiple vendors"-- , Includes bibliographical references and index

Language: English

Keywords: Grafikprozessor ; Bildverarbeitung ; Parallelverarbeitung ; Grafikprozessor ; CUDA ; Aufsatzsammlung

URL: Volltext

UID:

Format: xxviii, 551 Seiten : , Illustrationen, Diagramme (überwiegend farbig) ; , 24 cm.

Edition: Fourth edition

ISBN: 978-0-323-91231-0

Note: Literaturangaben

Language: English

Subjects: Computer Science

Keywords: Paralleles Programm ; Mehrprozessorsystem

UID:

Format: XX, 865 Seiten , Ill., graph. Darst.

Edition: Emerald ed.

ISBN: 9780123849885 , 9780123849885 , 0123849888

Series Statement: Applications of GPU computing series

Note: Text engl.

Language: English

Keywords: Grafikprozessor ; Parallelverarbeitung ; Bildverarbeitung

UID:

Format: Online Ressource (xvi, 541 p., [16] p. of plates) , ill. (some col.)

Edition: Jade ed.

Edition: Online-Ausg.

ISBN: 0123859638 , 9780123859631 , 9780123859648 , 0123859646 , 1283288206 , 9781283288200

Series Statement: Applications of GPU computing series

Content: "Since the introduction of CUDA in 2007, more than 100 million computers with CUDA capable GPUs have been shipped to end users. GPU computing application developers can now expect their application to have a mass market. With the introduction of OpenCL in 2010, researchers can now expect to develop GPU applications that can run on hardware from multiple vendors"--

Note: Includes bibliographical references and index. - Description based on print version record , Large-scale GPU searchEdge v. node parallelism for graph centrality metrics -- Optimizing parallel prefix operations for the Fermi architecture -- Building an efficient hash table on the GPU -- Efficient CUDA algorithms for the maximum network flow problem -- Optimizing memory access patterns for cellular automata on GPUs -- Fast minimum spanning tree computation -- Comparison-based in-place sorting with CUDA -- Interval arithmetic in CUDA -- Approximating the erfinv function -- A hybrid method for solving tridiagonal systems on the GPU -- Accelerating CULA linear algebra routines with hybrid GPU and multicore computing -- GPU accelerated derivative-free mesh optimization -- Large-scale gas turbine simulations on GPU clusters -- GPU acceleration of rarefied gas dynamic simulations -- Application of assembly of finite element methods on graphics processors for real-time elastodynamics -- CUDA implementation of vertex-centered, finite volume CFD methods on unstructured grids with flow control applications -- Solving wave equations on unstructured geometries -- Fast electromagnetic integral equation solvers on graphics processing units (GPUs) -- Solving large multibody dynamics problems on the GPU -- Implicit FEM solver on GPU for interactive deformation simulation -- Real-time adaptive GPU multiagent path planning -- Pricing financial derivatives with high performance finite difference solvers on GPUs -- Large-scale credit risk loss simulation -- Monte Carlo-based financial market value-at-risk estimation on GPUs --Thrust : a productivity-oriented library for CUDA -- GPU scripting and code generation with PyCUDA -- Jacket : GPU powered MATLAB acceleration -- Accelerating development and execution speed with just-in-time GPU code generation -- GPU application development, debugging, and performance tuning with GPU Ocelot -- Abstraction for AoS and SoA layout in C++ -- Processing device arrays with C++ metaprogramming -- GPU metaprogramming : a case study in biologically inspired machine vision -- A hybridization methodology for high-performance linear algebra software for GPUs -- Dynamic load balancing using work-stealing -- Applying software-managed caching and CPU/GPU task scheduling for accelerating dynamic workloads. , Machine generated contents note: Part 1: Parallel Algorithms and Data Structures -- Paulius Micikevicius, NVIDIA 1 Large-Scale GPU Search 2 Edge v. Node Parallelism for Graph Centrality Metrics 3 Optimizing parallel prefix operations for the Fermi architecture 4 Building an Efficient Hash Table on the GPU 5 An Efficient CUDA Algorithm for the Maximum Network Flow Problem 6 On Improved Memory Access Patterns for Cellular Automata Using CUDA 7 Fast Minimum Spanning Tree Computation on Large Graphs 8 Fast in-place sorting with CUDA based on bitonic sort Part 2: Numerical Algorithms -- Frank Jargstorff, NVIDIA 9 Interval Arithmetic in CUDA 10 Approximating the erfinv Function 11 A Hybrid Method for Solving Tridiagonal Systems on the GPU 12 LU Decomposition in CULA 13 GPU Accelerated Derivative-free Optimization Part 3: Engineering Simulation -- Peng Wang, NVIDIA 14 Large-scale gas turbine simulations on GPU clusters 15 GPU acceleration of rarefied gas dynamic simulations 16 Assembly of Finite Element Methods on Graphics Processors 17 CUDA implementation of Vertex-Centered, Finite Volume CFD methods on Unstructured Grids with Flow Control Applications 18 Solving Wave Equations on Unstructured Geometries 19 Fast electromagnetic integral equation solvers on graphics processing units (GPUs) Part 4: Interactive Physics for Games and Engineering Simulation -- Richard Tonge, NVIDIA 20 Solving Large Multi-Body Dynamics Problems on the GPU 21 Implicit FEM Solver in CUDA 22 Real-time Adaptive GPU multi-agent path planning Part 5: Computational Finance -- Thomas Bradley, NVIDIA 23 High performance finite difference PDE solvers on GPUs for financial option pricing 24 Identifying and Mitigating Credit Risk using Large-scale Economic Capital Simulations 25 Financial Market Value-at-Risk Estimation using the Monte Carlo Method Part 6: Programming Tools and Techniques -- Cliff Wooley, NVIDIA 26 Thrust: A Productivity-Oriented Library for CUDA 27 GPU Scripting and Code Generation with PyCUDA 28 Jacket: GPU Powered MATLAB Acceleration 29 Accelerating Development and Execution Speed with Just In Time GPU Code Generation 30 GPU Application Development, Debugging, and Performance Tuning with GPU Ocelot 31 Abstraction for AoS and SoA Layout in C++ 32 Processing Device Arrays with C++ Metaprogramming 33 GPU Metaprogramming: A Case Study in Biologically-Inspired Machine Vision 34 A Hybridization Methodology for High-Performance Linear Algebra Software for GPUs 35 Dynamic Load Balancing using Work-Stealing 36 Applying software-managed caching and CPU/GPU task scheduling for accelerating dynamic workloads. , Part 1: Parallel Algorithms and Data Structures - Paulius Micikevicius, NVIDIA 1 Large-Scale GPU Search 2 Edge v. Node Parallelism for Graph Centrality Metrics 3 Optimizing parallel prefix operations for the Fermi architecture 4 Building an Efficient Hash Table on the GPU 5 An Efficient CUDA Algorithm for the Maximum Network Flow Problem 6 On Improved Memory Access Patterns for Cellular Automata Using CUDA 7 Fast Minimum Spanning Tree Computation on Large Graphs 8 Fast in-place sorting with CUDA based on bitonic sort Part 2: Numerical Algorithms - Frank Jargstorff, NVIDIA 9 Interval Arithmetic in CUDA 10 Approximating the erfinv Function 11 A Hybrid Method for Solving Tridiagonal Systems on the GPU 12 LU Decomposition in CULA 13 GPU Accelerated Derivative-free Optimization Part 3: Engineering Simulation - Peng Wang, NVIDIA 14 Large-scale gas turbine simulations on GPU clusters 15 GPU acceleration of rarefied gas dynamic simulations 16 Assembly of Finite Element Methods on Graphics Processors 17 CUDA implementation of Vertex-Centered, Finite Volume CFD methods on Unstructured Grids with Flow Control Applications 18 Solving Wave Equations on Unstructured Geometries 19 Fast electromagnetic integral equation solvers on graphics processing units (GPUs) Part 4: Interactive Physics for Games and Engineering Simulation - Richard Tonge, NVIDIA 20 Solving Large Multi-Body Dynamics Problems on the GPU 21 Implicit FEM Solver in CUDA 22 Real-time Adaptive GPU multi-agent path planning Part 5: Computational Finance - Thomas Bradley, NVIDIA 23 High performance finite difference PDE solvers on GPUs for financial option pricing 24 Identifying and Mitigating Credit Risk using Large-scale Economic Capital Simulations 25 Financial Market Value-at-Risk Estimation using the Monte Carlo Method Part 6: Programming Tools and Techniques - Cliff Wooley, NVIDIA 26 Thrust: A Productivity-Oriented Library for CUDA 27 GPU Scripting and Code Generation with PyCUDA 28 Jacket: GPU Powered MATLAB Acceleration 29 Accelerating Development and Execution Speed with Just In Time GPU Code Generation 30 GPU Application Development, Debugging, and Performance Tuning with GPU Ocelot 31 Abstraction for AoS and SoA Layout in C++ 32 Processing Device Arrays with C++ Metaprogramming 33 GPU Metaprogramming: A Case Study in Biologically-Inspired Machine Vision 34 A Hybridization Methodology for High-Performance Linear Algebra Software for GPUs 35 Dynamic Load Balancing using Work-Stealing 36 Applying software-managed caching and CPU/GPU task scheduling for accelerating dynamic workloads.

Additional Edition: ISBN 0123859646

Additional Edition: ISBN 1283288206

Additional Edition: Druckausg. GPU computing gems Waltham, MA : Morgan Kaufmann, 2012 ISBN 9780123859631

Additional Edition: ISBN 0123859638

Language: English

Keywords: Grafikprozessor ; Bildverarbeitung ; Parallelverarbeitung ; Electronic books ; Electronic books ; Electronic books

URL: lizenzpflichtig

URL: Volltext

UID:

Format: Online Ressource (xx, 865 p.) , ill.

Edition: Emerald ed.

Edition: Online-Ausg. Amsterdam [u.a.] Elsevier Online-Ressource

ISBN: 9780123849885 , 0123849888 , 0123849896 , 9780123849892

Series Statement: Applications of GPU computing

Content: -- Scientific Simulation -- Life Sciences -- Statistical Modeling -- Emerging Data-Intensive Applications -- Electronic Design Automation -- Ray Tracing and Rendering -- Computer Vision -- Video and Image Processing -- Signal and Audio Processing -- Medical Imaging

Content: " ... the perfect companion to Programming Massively Parallel Processors by Hwu & Kirk."--Nicolas Pinto, Research Scientist at Harvard & MIT, NVIDIA Fellow 2009-2010 Graphics Processing Units (GPUs) are designed to be parallel - having hundreds of cores versus traditional CPUs. Increasingly, you can leverage GPU power for many computationally-intense applications - not just for graphics. If you're facing the challenge of programming systems to effectively use these massively parallel processors to achieve efficiency and performance goals, GPU Computing Gems provides a wealth of tested, proven GPU techniques. Different application domains often pose similar algorithm problems, and researchers from diverse application domains often develop similar algorithmic strategies. GPU Computing Gems offers developers a window into diverse application areas, and the opportunity to gain insights from others' algorithm work that they may apply to their own projects. Learn from the leading researchers in parallel programming, who have gathered their solutions and experience in one volume under the guidance of expert area editors. Each chapter is written to be accessible to researchers from other domains, allowing knowledge to cross-pollinate across the GPU spectrum. GPU Computing Gems: Emerald Edition is the first volume in Morgan Kaufmann's Applications of GPU Computing Series, offering the latest insights and research in computer vision, electronic design automation, emerging data-intensive applications, life sciences, medical imaging, ray tracing and rendering, scientific simulation, signal and audio processing, statistical modeling, video and image processing. Covers the breadth of industry from scientific simulation and electronic design automation to audio / video processing, medical imaging, computer vision, and more Many examples leverage NVIDIA's CUDA parallel computing architecture, the most widely-adopted massively parallel programming solution Offers insights and ideas as well as practical "hands-on" skills you can immediately put to use

Note: Includes bibliographical references and index , -- Scientific Simulation -- Life Sciences -- Statistical Modeling -- Emerging Data-Intensive Applications -- Electronic Design Automation -- Ray Tracing and Rendering -- Computer Vision -- Video and Image Processing -- Signal and Audio Processing -- Medical Imaging. , " ... the perfect companion to Programming Massively Parallel Processors by Hwu & Kirk."--Nicolas Pinto, Research Scientist at Harvard & MIT, NVIDIA Fellow 2009-2010 Graphics Processing Units (GPUs) are designed to be parallel - having hundreds of cores versus traditional CPUs. Increasingly, you can leverage GPU power for many computationally-intense applications - not just for graphics. If you're facing the challenge of programming systems to effectively use these massively parallel processors to achieve efficiency and performance goals, GPU Computing Gems provides a wealth of tested, proven GPU techniques. Different application domains often pose similar algorithm problems, and researchers from diverse application domains often develop similar algorithmic strategies. GPU Computing Gems offers developers a window into diverse application areas, and the opportunity to gain insights from others' algorithm work that they may apply to their own projects. Learn from the leading researchers in parallel programming, who have gathered their solutions and experience in one volume under the guidance of expert area editors. Each chapter is written to be accessible to researchers from other domains, allowing knowledge to cross-pollinate across the GPU spectrum. GPU Computing Gems: Emerald Edition is the first volume in Morgan Kaufmann's Applications of GPU Computing Series, offering the latest insights and research in computer vision, electronic design automation, emerging data-intensive applications, life sciences, medical imaging, ray tracing and rendering, scientific simulation, signal and audio processing, statistical modeling, video and image processing. Covers the breadth of industry from scientific simulation and electronic design automation to audio

Additional Edition: ISBN 9780123849885

Additional Edition: ISBN 0123849888

Additional Edition: ISBN 9780123849885

Additional Edition: Druckausg. GPU computing gems Amsterdam : Morgan Kaufmann, 2011 ISBN 0123849888

Additional Edition: ISBN 9780123849885

Language: English

Subjects: Computer Science

Keywords: Computergrafik ; Echtzeitverarbeitung ; Programmierung ; Electronic books ; Electronic books ; Electronic books

URL: lizenzpflichtig

URL: Volltext

URL: Inhaltsverzeichnis