In:
IEEE Transactions on Circuits and Systems-I: Fundamental Theory..., March, 2001, Vol.48(3), p.382
Description:
This paper and its companion (Part I) are devoted to to the analysis of the application of a chaotic piecewise-linear one-dimensional (PL1D) map as Random Number Generator (RNG). In Part I, we have mathematically analyzed the information generation process of a class of PL1D maps. In this paper, we find optimum parameters that give an RNG with lowest redundancy and maximum margin against parasitic attractors. Further, the map is implemented in a 0.8 [micro]]m standard CMOS process utilizing switched current techniques. Post-layout circuit simulations of the RNG indicate no periodic attractors over variations in temperature, power supply and process conditions, and maximum redundancy of 0.4%. We estimate that the output bit rate of our RNG is 1 Mbit/s, which is substantially higher than the output bit rate of RNGs available on the market. Index Terms--Chaos, CMOS, random number generator.
Keywords:
Random Number Generators (Software) -- Models ; Complementary Metal Oxide Semiconductors -- Usage ; Chaotic Systems -- Usage
ISSN:
1057-7122
E-ISSN:
15581268
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