1659351901

System Reduction for Nanoscale IC Design / edited by Peter Benner

Englisch

Cham : Springer, 2017

Online-Ressource (XI, 197 p. 73 illus., 39 illus. in color, online resource)

Druckausg.: ISBN 978-3-319-07235-7

Erscheint auch als: Druck-Ausgabe- Benner, Peter *1967-*: System reduction for nanoscale IC design. - Cham, Switzerland : Springer Nature, 2017. - xi, 197 Seiten

978-3-319-07236-4

Weitere Ausgaben: 978-3-319-07235-7 (Druckausgabe)

DOI: 10.1007/978-3-319-07236-4

*Schaltungsentwurf / Ordnungsreduktion

*Mathematics ; Computer science ; Computer aided design ; Computer-aided engineering ; Computer mathematics ; Mathematical models ; Applied mathematics ; Microelectronics ; Algorithms ; Engineering mathematics ; Electronics ; Mathematics ; Computer-aided engineering ; Algorithms ; Computer mathematics ; Mathematical models ; Applied mathematics ; Engineering mathematics ; Electronics ; Microelectronics

*Electronic circuit design ; Nanoelectronics

Klassifikation der Library of Congress: QA71-90

Dewey Dezimal-Klassifikation: 004;

bisacsh: MAT003000

Mathematics Subject Classification: *65-06

Mathematics Subject Classification: 00A69

Mathematics Subject Classification: 65Z05

Book Industry Communication: PDE

bisacsh: COM014000

Preface -- 1 Model order reduction of integrated circuits in electrical networks: Michael Hinze, Martin Kunkel, Ulrich Matthes, and Morten Vierling -- 2 Element-based model reduction in circuit simulation: Andreas Steinbrecher and Tatjana Stykel -- 3 Reduced Representation of Power Grid Models: Peter Benner and André Schneider -- 4 Coupling of numeric/symbolic reduction methods for generating parametrized models of nanoelectronic systems: Oliver Schmidt, Matthias Hauser, and Patrick Lang -- 5 Low-Rank Cholesky Factor Krylov Subspace Methods for Generalized Projected Lyapunov Equations: Matthias Bollhöfer and André K. Eppler -- Index

This book describes the computational challenges posed by the progression toward nanoscale electronic devices and increasingly short design cycles in the microelectronics industry, and proposes methods of model reduction which facilitate circuit and device simulation for specific tasks in the design cycle. The goal is to develop and compare methods for system reduction in the design of high dimensional nanoelectronic ICs, and to test these methods in the practice of semiconductor development. Six chapters describe the challenges for numerical simulation of nanoelectronic circuits and suggest model reduction methods for constituting equations. These include linear and nonlinear differential equations tailored to circuit equations and drift diffusion equations for semiconductor devices. The performance of these methods is illustrated with numerical experiments using real-world data. Readers will benefit from an up-to-date overview of the latest model reduction methods in computational nanoelectronics

https://zbmath.org/?q=an:1367.65003 [Zentralblatt MATH]

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https://doi.org/10.1007/978-3-319-07236-4 [E-books (Springer)]