UID:
almafu_9960074044102883
Umfang:
1 online resource (466 p.)
Ausgabe:
1st edition
ISBN:
9780128101339
,
0128101334
,
9780124095298
,
0124095291
Inhalt:
For those with a basic understanding of digital design, this book teaches the essential skills to design digital integrated circuits using Verilog and the relevant extensions of SystemVerilog. In addition to covering the syntax of Verilog and SystemVerilog, the author provides an appreciation of design challenges and solutions for producing working circuits. The book covers not only the syntax and limitations of HDL coding, but deals extensively with design problems such as partitioning and synchronization, helping you to produce designs that are not only logically correct, but will actually
Anmerkung:
Description based upon print version of record.
,
Cover; Title Page; Copyright Page; Table of contents; About the author; Preface; Acknowledgments; Chapter 1 - Introduction; Who should read this book; Hardware description languages and methodology; What this Book Covers; Historical Perspective; Verilog and Systemverilog; Book Organization; Chapter 2 - Bottom-up design; Primitive instantiation; Designing with primitives; Identifiers and escaped identifiers; Bus declarations; Design hierarchy and test fixtures; Port association; Timescales; Summary; Chapter 3 - Behavioral coding part I: blocks, variables, and operators; Top-down design
,
Synthesizable and nonsynthesizable codeRegister Transfer Level (RTL); Continuous assignments; Implicit continuous assignments; Functional blocks: always and initial; Named blocks; Sensitivity lists; Splitting assignments; Variables; Nets; Net aliases; Net signal strength; Registers; SystemVerilog variables; Var variables; Arrays; Bidirectional buses; Structures and unions; Operators; Assignment operators; Equality operators; Logical operators; Bitwise operators; Reduction operators; Arithmetic operators; Auto increment and auto decrement; Relational operators; Shift operators
,
Concatenation operatorReplication operator; Conditional operator; SystemVerilog combined assignment operators; Operator precedence; Summary; Chapter 4 - Behavioral coding part II: defines, parameters, enumerated types, and packages; Global Definitions; Parameters; Overriding Default Values; Local Parameters; Specify parameters; Enumerated Types; Constants; Packages; Filling a Scalable Variable with All Ones; Summary; Reference; Chapter 5 - Behavioral coding part III: loops and branches; Loops; While loop; Do while loop; For loop; Foreach loop; Forever loop; Repeat loop; Break and continue
,
DisableGenerate; Multiway branching; If statements; Case statements; Latch generation; Unique and priority; Summary; Reference; Chapter 6 - Subroutines and interfaces; Subroutines; Tasks; Functions; Parameters in subroutines; Managing subroutines; Interfaces; Interface modports; Summary; Chapter 7 - Synchronization; Latch instability; Flipflops, latches, and violations; Asynchronous assert, synchronous deassert; Slow-speed single-bit clocked asynchronous interfaces; High-speed single-bit clocked asynchronous interfaces; Multiple high-speed single-bit clocked asynchronous interfaces
,
Asynchronous parallel busesFIFO; FIFO operation and throughput; FIFO depth; High-speed asynchronous serial links; Summary; References; Chapter 8 - Simulation, timing, and race conditions; Simulation queues; Race conditions; Derived clocks and delta time; Assertions; Summary; References; Chapter 9 - Architectural choices; FPGA versus ASIC; Design reuse; Partitioning; Area and speed optimization; Power optimization; Summary; References; Chapter 10 - Design for testability; Yield, testing, and defect level; Fault modeling; Activation and sensitization; Logic scan; Boundary scan
,
Built in self-test
,
English
Weitere Ausg.:
ISBN 9780124080591
Weitere Ausg.:
ISBN 0124080596
Weitere Ausg.:
ISBN 9781322183992
Weitere Ausg.:
ISBN 1322183996
Sprache:
Englisch
Bookmarklink
