UID:
almahu_9948621307502882
Format:
XII, 297 p.
,
online resource.
Edition:
1st ed. 2004.
ISBN:
9781441989871
Content:
Today, the more rapid rate of speed increase in microprocessor technology than in memory has created a serious memory gap (or "wall") for computer designers and manufacturers. Edited by leading international authorities in the field, High Performance Memory Systems surveys advances in technology, architecture, and algorithms that address both scalability needs in multiprocessors and the expanding gap between CPU/network and memory speeds. The range of approaches described here address issues present on uni-processor systems as well as on multi-processor systems. Current research highlights from both industry and academia focus on: coherence, synchronization, and allocation; power-awareness, reliability, and reconfigurability; software-based memory tuning; architecture design issues; and workload considerations. Topics and features: * Describes leading-edge research relevant to the growing disparity between CPU and memory speed * Provides theoretical and practical approaches to the memory-wall problem, including some from recent worldwide symposiums on the topic * Includes specific solutions to common problems in different operating environments * Offers a broad overview of high performance memory systems, as well as in-depth discussions of select, essential areas * Includes a concise, thorough introductory chapter about the field This unique and comprehensive compendium assembles the work by leading researchers and professionals into aspects of improving the memory-system performance of general-purpose programs. It is ideally suited for researchers and R&D professionals with interests, or practice, in computer engineering, computer architecture, memory design, and general processor architecture.
Note:
1 Introduction to High-Performance Memory Systems - scan all -- 1.1 Coherence, Synchronization, and Allocation -- 1.2 Power-Aware, Reliable, and Reconfigurable Memory -- 1.3 Software-Based Memory Tuning -- 1.4 Architecture-Based Memory Tuning -- 1.5 Workload Considerations -- I Coherence, Synchronization, and Allocation -- 2 Speculative Locks: Concurrent Execution of Critical Sections in Shared-Memory Multiprocessors -- 3 Dynamic Verification of Cache Coherence Protocols -- 4 Timestamp-Based Selective Cache Allocation -- II Power-Aware, Reliable, and Reconfigurable Memory -- 5 Power-Efficient Cache Coherence -- 6 Improving Power Efficiency with an Asymmetric Set-Associative Cache -- 7 Memory Issues in Hardware-Supported Software Safety -- 8 Reconfigurable Memory Module in the RAMP System for Stream Processing -- III Software-Based Memory Tuning -- 9 Performance of Memory Expansion Technology (MXT) -- 10 Profile-Tuned Heap Access -- 11 Array Merging: A Technique for Improving Cache and TLB Behavior -- 12 Software Logging under Speculative Parallelization -- IV Architecture-Based Memory Tuning -- 13 An Analysis of Scalar Memory Accesses in Embedded and Multimedia Systems -- 14 Bandwidth-Based Prefetching for Constant-Stride Arrays -- 15 Performance Potential of Effective Address Prediction of Load Instructions -- V Workload Considerations -- 16 Evaluating Novel Memory System Alternatives for Speculative Multithreaded Computer Systems -- 17 Evaluation of Large L3 Caches Using TPC-H Trace Samples -- 18 Exploiting Intelligent Memory for Database Workloads -- Author Index.
In:
Springer Nature eBook
Additional Edition:
Printed edition: ISBN 9781461264774
Additional Edition:
Printed edition: ISBN 9780387003108
Additional Edition:
Printed edition: ISBN 9781441989888
Language:
English
DOI:
10.1007/978-1-4419-8987-1
URL:
https://doi.org/10.1007/978-1-4419-8987-1
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