Format:
1 Online-Ressource (375 pages)
ISBN:
076950325X
,
9780769503257
Content:
Papers from a November 1999 symposium cover areas of yield, testing techniques, built-in self-test architectures, fault modeling and simulation, design for testing, self-checking processing units and systems, self-checking memories and interconnections, diagnosis, and reconfiguration. Specific topics include a zero aliasing built-in self-test technique for delay fault testing, novel control pattern generators for interconnect testing with boundary scan, optimal vector selection for low power BIST, and fast signature simulation for PPSFP simulators. Other topics are erasure error correction with hardware correction, and reconfiguration of two-dimensional meshes embedded in faulty hypercubes. Lacks a subject index. Annotation copyrighted by Book News, Inc., Portland, OR
Language:
English
Keywords:
Konferenzschrift
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