UID:
almafu_9959327359302883
Format:
1 online resource.
ISBN:
9781118703335
,
1118703332
,
9781118703342
,
1118703340
,
9781118703328
,
1118703324
,
9781299831124
,
1299831125
,
1118511883
,
9781118511886
Series Statement:
ESD series
Content:
"Electrical Overstress (EOS) continues to impact semiconductor manufacturing, semiconductor components and systems as technologies scale from micro- to nano-electronics. This bookteaches the fundamentals of electrical overstress and how to minimize and mitigate EOS failures. The text provides a clear picture of EOS phenomena, EOS origins, EOS sources, EOS physics, EOS failure mechanisms, and EOS on-chip and system design. It provides an illuminating insight into the sources of EOS in manufacturing, integration of on-chip, and system level EOS protection networks, followed by examples in specific technologies, circuits, and chips. The book is unique in covering the EOS manufacturing issues from on-chip design and electronic design automation to factory-level EOS program management in today's modern world. Look inside for extensive coverage on: Fundamentals of electrical overstress, from EOS physics, EOS time scales, safe operating area (SOA), to physical models for EOS phenomena EOS sources in today's semiconductor manufacturing environment, and EOS program management, handling and EOS auditing processing to avoid EOS failures EOS failures in both semiconductor devices, circuits and system Discussion of how to distinguish between EOS events, and electrostatic discharge (ESD) events (e.g. such as human body model (HBM), charged device model (CDM), cable discharge events (CDM), charged board events (CBE), to system level IEC 61000-4-2 test events) EOS protection on-chip design practices and how they differ from ESD protection networks and solutions Discussion of EOS system level concerns in printed circuit boards (PCB), and manufacturing equipment Examples of EOS issues in state-of-the-art digital, analog and power technologies including CMOS, LDMOS, and BCD EOS design rule checking (DRC), LVS, and ERC electronic design automation (EDA) and how it is distinct from ESD EDA systems EOS testing and qualification techniques, and Practical off-chip ESD protection and system level solutions to provide more robust systems Electrical Overstress (EOS): Devices, Circuits and Systems is a continuation of the author's series of books on ESD protection. It is an essential reference and a useful insight into the issues that confront modern technology as we enter the nano-electronic era"--
Content:
"This book addresses EOS phenomena and distinguish it from other forms of phenomena such as electrostatic discharge (ESD), latchup, and EMC events"--
Note:
Electrical Overstress (EOS): Devices, Circuits and Systems -- Contents -- About the Author -- Preface -- Acknowledgements -- 1 Fundamentals of Electrical Overstress -- 1.1 Electrical Overstress -- 1.1.1 The Cost of Electrical Overstress -- 1.1.2 Product Field Returns -- The Percentage that is Electrical Overstress -- 1.1.3 Product Field Returns -- No Defect Found versus Electrical Overstress -- 1.1.4 Product Failures -- Failures in Integrated Circuits -- 1.1.5 Classification of Electrical Overstress Events -- 1.1.6 Electrical Over-Current -- 1.1.7 Electrical Over-Voltage -- 1.1.8 Electrical Over-Power -- 1.2 De-Mystifying Electrical Overstress -- 1.2.1 Electrical Overstress Events -- 1.3 Sources of Electrical Overstress -- 1.3.1 Sources of Electrical Overstress in Manufacturing Environment -- 1.3.2 Sources of Electrical Overstress in Production Environments -- 1.4 Misconceptions of Electrical Overstress -- 1.5 Minimization of Electrical Overstress Sources -- 1.6 Mitigation of Electrical Overstress -- 1.7 Signs of Electrical Overstress Damage -- 1.7.1 Signs of Electrical Overstress Damage -- The Electrical Signature -- 1.7.2 Signs of Electrical Overstress Damage -- The Visual Signature -- 1.8 Electrical Overstress and Electrostatic Discharge -- 1.8.1 Comparison of High and Low Current EOS versus ESD Events -- 1.8.2 Electrical Overstress and Electrostatic Discharge Differences -- 1.8.3 Electrical Overstress and Electrostatic Discharge Similarities -- 1.8.4 Comparison of EOS versus ESDWaveforms -- 1.8.5 Comparison of EOS versus ESD Event Failure Damage -- 1.9 Electromagnetic Interference -- 1.9.1 Electrical Overstress Induced Electromagnetic Interference -- 1.10 Electromagnetic Compatibility -- 1.11 Thermal Over-Stress -- 1.11.1 Electrical Overstress and Thermal Overstress -- 1.11.2 Temperature Dependent Electrical Overstress.
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1.11.3 Electrical Overstress and Melting Temperature -- 1.12 Reliability Technology Scaling -- 1.12.1 Reliability Technology Scaling and the Reliability Bathtub Curve -- 1.12.2 The Shrinking Reliability Design Box -- 1.12.3 The Shrinking Electrostatic Discharge Design Box -- 1.12.4 Application Voltage, Trigger Voltage, and Absolute Maximum Voltage -- 1.13 Safe Operating Area -- 1.13.1 Electrical Safe Operating Area -- 1.13.2 Thermal Safe Operating Area -- 1.13.3 Transient Safe Operating Area -- 1.14 Summary and Closing Comments -- References -- 2 Fundamentals of EOS Models -- 2.1 Thermal Time Constants -- 2.1.1 The Thermal Diffusion Time -- 2.1.2 The Adiabatic Regime Time Constant -- 2.1.3 The Thermal Diffusion Regime Time Constant -- 2.1.4 The Steady State Regime Time Constant -- 2.2 Pulse Event Time Constants -- 2.2.1 The ESD HBM Pulse Time Constant -- 2.2.2 The ESD MM Pulse Time Constant -- 2.2.3 The ESD Charged Device Model Pulse Time Constant -- 2.2.4 The ESD Pulse Time Constant -- Transmission Line Pulse -- 2.2.5 The ESD Pulse Time Constant -- Very Fast Transmission Line Pulse -- 2.2.6 The IEC 61000-4-2 Pulse Time Constant -- 2.2.7 The Cable Discharge Event Pulse Time Constant -- 2.2.8 The IEC 61000-4-5 Pulse Time Constant -- 2.3 Mathematical Methods for EOS -- 2.3.1 Mathematical Methods for EOS -- Green's Functions -- 2.3.2 Mathematical Methods for EOS -- Method of Images -- 2.3.3 Mathematical Methods for EOS -- Thermal Diffusion Partial Differential Equation -- 2.3.4 Mathematical Methods for EOS -- Thermal Diffusion Partial Differential Equation with Variable Coefficients -- 2.3.5 Mathematical Methods for EOS -- Duhamel Formulation -- 2.3.6 Mathematical Methods for EOS -- Integral Transforms of the Heat Conduction Equation -- 2.4 The Spherical Model -- Tasca Derivation -- 2.4.1 The Tasca Model in the ESD Time Regime.
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2.4.2 The Tasca Model in the EOS Time Regime -- 2.4.3 The Vlasov-Sinkevitch Model -- 2.5 The One-dimensional Model -- Wunsch-Bell Derivation -- 2.5.1 The Wunsch-Bell Curve -- 2.5.2 The Wunsch-Bell Model in the ESD Time Regime -- 2.5.3 The Wunsch-Bell Model in the EOS Time Regime -- 2.6 The Ash Model -- 2.7 The Cylindrical Model -- The Arkihpov-Astvatsaturyan- Godovosyn-Rudenko Derivation -- 2.8 The Three-dimensional Parallelepiped Model -- Dwyer- Franklin-Campbell Derivation -- 2.8.1 The Dwyer-Franklin-Campbell Model in the ESD Time Regime -- 2.8.2 The Dwyer-Campbell-Franklin Model in the EOS Time Regime -- 2.9 The Resistor Model -- Smith-Littau Derivation -- 2.10 Instability -- 2.10.1 Electrical Instability -- 2.10.2 Electrical Breakdown -- 2.10.3 Electrical Instability and Snapback -- 2.10.4 Thermal Instability -- 2.11 Electro-migration and Electrical Overstress -- 2.12 Summary and Closing Comments -- References -- 3 EOS, ESD, EMI, EMC and Latchup -- 3.1 Electrical Overstress Sources -- 3.1.1 EOS Sources -- Lightning -- 3.1.2 EOS Sources -- Power Distribution -- 3.1.3 EOS Sources -- Switches, Relays, and Coils -- 3.1.4 EOS Sources -- Switch Mode Power Supplies -- 3.1.5 EOS Sources -- Machinery -- 3.1.6 EOS Sources -- Actuators -- 3.1.7 EOS Sources -- Solenoids -- 3.1.8 EOS Sources -- Servo Motors -- 3.1.9 EOS Sources -- Variable Frequency Drive Motors -- 3.1.10 EOS Sources -- Cables -- 3.2 EOS Failure Mechanisms -- 3.2.1 EOS Failure Mechanisms: Semiconductor Process -- Application Mismatch -- 3.2.2 EOS Failure Mechanisms: Bond Wire Failure -- 3.2.3 EOS Failure Mechanisms: PCB to Chip Failures -- 3.2.4 EOS Failure Mechanisms: External Load to Chip Failures -- 3.2.5 EOS Failure Mechanisms: Reverse Insertion Failures -- 3.3 Failure Mechanism -- Latchup or EOS? -- 3.3.1 Latchup versus EOS Design Window -- 3.4 Failure Mechanism -- Charged Board Model or EOS?
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3.5 Summary and Closing Comments -- References -- 4 EOS Failure Analysis -- 4.1 Electrical Overstress Failure Analysis -- 4.1.1 EOS Failure Analysis -- Information Gathering and Fact Finding -- 4.1.2 EOS Failure Analysis -- Failure Analysis Report and Documentation -- 4.1.3 EOS Failure Analysis -- Failure Site Localization -- 4.1.4 EOS Failure Analysis -- Root Cause Analysis -- 4.1.5 EOS or ESD Failure Analysis -- Can Visual Failure Analysis Tell the Difference? -- 4.2 EOS Failure Analysis -- Choosing the Correct Tool -- 4.2.1 EOS Failure Analysis -- Non-Destructive Methods -- 4.2.2 EOS Failure Analysis -- Destructive Methods -- 4.2.3 EOS Failure Analysis -- Differential Scanning Calorimetry -- 4.2.4 EOS Failure Analysis -- Scanning Electron Microscope/Energy Dispersive X-ray Spectroscopy -- 4.2.5 EOS Failure Analysis -- Fourier Transform Infrared Spectroscopy -- 4.2.6 EOS Failure Analysis -- Ion Chromatography -- 4.2.7 EOS Failure Analysis -- Optical Microscopy -- 4.2.8 EOS Failure Analysis -- Scanning Electron Microscopy -- 4.2.9 EOS Failure Analysis -- Transmission Electron Microscopy -- 4.2.10 EOS Failure Analysis -- Emission Microscope Tool -- 4.2.11 EOS Failure Analysis -- Voltage Contrast Tools -- 4.2.12 EOS Failure Analysis -- IR Thermography -- 4.2.13 EOS Failure Analysis -- Optical Beam Induced Resistance Change Tool -- 4.2.14 EOS Failure Analysis -- IR-OBIRCH Tool -- 4.2.15 EOS Failure Analysis -- Thermally Induced Voltage Alteration Tool -- 4.2.16 EOS Failure Analysis -- Atomic Force Microscope Tool -- 4.2.17 EOS Failure Analysis -- Super-Conducting Quantum Interference Device Microscope -- 4.2.18 EOS Failure Analysis -- Picosecond Imaging Current Analysis Tool -- 4.3 Summary and Closing Comments -- References -- 5 EOS Testing and Simulation -- 5.1 Electrostatic Discharge Testing -- Component Level -- 5.1.1 ESD Testing -- Human Body Model.
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5.1.2 ESD Testing -- Machine Model -- 5.1.3 ESD Testing -- Charged Device Model -- 5.2 Transmission Line Pulse Testing -- 5.2.1 ESD Testing -- Transmission Line Pulse -- 5.2.2 ESD Testing -- Very Fast Transmission Line Pulse -- 5.3 ESD Testing -- System Level -- 5.3.1 ESD System Level Testing -- IEC 61000-4-2 -- 5.3.2 ESD Testing -- Human Metal Model -- 5.3.3 ESD Testing -- Charged Board Model -- 5.3.4 ESD Testing -- Cable Discharge Event -- 5.4 Electrical Overstress Testing -- 5.4.1 EOS Testing -- Component Level -- 5.4.2 EOS Testing -- System Level -- 5.5 EOS Testing -- Lightning -- 5.6 EOS Testing -- IEC 61000-4-5 -- 5.7 EOS Testing -- Transmission Line Pulse Method and EOS -- 5.7.1 EOS Testing -- Long Pulse TLP Method -- 5.7.2 EOS Testing -- TLP Method, EOS and the Wunsch-Bell Model -- 5.7.3 EOS Testing -- Limitations of the TLP Method for the Evaluation of EOS for Systems -- 5.7.4 EOS Testing -- Electro-magnetic Pulse -- 5.8 EOS Testing -- D.C. and Transient Latchup -- 5.9 EOS Testing -- Scanning Methodologies -- 5.9.1 EOS Testing -- Susceptibility and Vulnerability -- 5.9.2 EOS Testing -- Electrostatic Discharge/Electromagnetic Compatibility Scanning -- 5.9.3 Electromagnetic Interference Emission Scanning Methodology -- 5.9.4 Radio Frequency Immunity Scanning Methodology -- 5.9.5 Resonance Scanning Methodology -- 5.9.6 Current Spreading Scanning Methodology -- 5.10 Summary and Closing Comments -- References -- 6 EOS Robustness -- Semiconductor Technologies -- 6.1 EOS and CMOS Technology -- 6.1.1 CMOS Technology -- Structures -- 6.1.2 CMOS Technology -- Safe Operation Area -- 6.1.3 CMOS Technology -- EOS and ESD Failure Mechanisms -- 6.1.4 CMOS Technology -- Protection Circuits -- 6.1.5 CMOS Technology -- Silicon On Insulator -- 6.1.6 CMOS Technology -- Latchup -- 6.2 EOS and RF CMOS and Bipolar Technology -- 6.2.1 RF CMOS and Bipolar Technology -- Structures.
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6.2.2 RF CMOS and Bipolar Technology -- Safe Operation Area.
Additional Edition:
Print version: Voldman, Steven H. Electrical overstress (EOS). Chichester, West Sussex, United Kingdom : John Wiley & Sons Inc., 2013 ISBN 9781118511886
Language:
English
Keywords:
Electronic books.
;
Electronic books.
URL:
https://onlinelibrary.wiley.com/doi/book/10.1002/9781118703328
URL:
https://onlinelibrary.wiley.com/doi/book/10.1002/9781118703328
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