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  • 1
    Online-Ressource
    Online-Ressource
    Boston : Kluwer Academic Publishers
    UID:
    b3kat_BV035413607
    Umfang: 1 Online-Ressource (xviii, 291 Seiten) , Illustrationen , 25 cm
    Ausgabe: 3rd ed
    Ausgabe: Online_Ausgabe Boulder, Colo NetLibrary 2003 E-Books von NetLibrary Sonstige Standardnummer des Gesamttitels: 22382847
    ISBN: 0306476401
    Anmerkung: Includes bibliographical references (p. [285]-286) and index
    Weitere Ausg.: Reproduktion von Keating, Michael Reuse methodology manual for system-on-a-chip designs 2002
    Sprache: Englisch
    Fachgebiete: Technik
    RVK:
    Schlagwort(e): System-on-Chip ; Entwurf ; VHDL ; Softwarewiederverwendung ; Electronic books. ; Electronic books.
    URL: Volltext  (Deutschlandweit zugänglich)
    URL: Cover
    URL: Full text  (Click to View (Currently Only Available on Campus))
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 2
    Online-Ressource
    Online-Ressource
    Boston : Kluwer Academic Publishers
    UID:
    gbv_1682132269
    Umfang: Online-Ressource
    Ausgabe: 3rd ed
    ISBN: 0306476401 , 9780306476402
    Serie: EBSCOhost eBook Collection
    Inhalt: Features of the Third Edition: UP TO DATE STATE OF THE ART REUSE AS A SOLUTION FOR CIRCUIT DESIGNERS A CHRONICLE OF "BEST PRACTICES" ALL CHAPTERS UPDATED AND REVISED GENERIC GUIDELINES-NON TOOL SPECIFIC EMPHASIS ON HARD IP AND PHYSICAL DESIGN Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips. In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality. From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques
    Anmerkung: Includes bibliographical references (p. [285]-286) and index , 1. Introduction2. The System-on-Chip Design Process -- 3. System-Level Design Issues: Rules and Tools -- 4. The Macro Design Process -- 5. RTL Coding Guidelines -- 6. Macro Synthesis Guidelines -- 7. Macro Verification Guidelines -- 8. Developing Hard Macros -- 9. Macro Deployment: Packaging for Reuse -- 10. System Integration with Reusable Macros -- 11. System-Level Verification Issues -- 12. Data and Project Management -- 13. Implementing Reuse-Based SoC Designs -- Bibliography -- Index.
    Weitere Ausg.: ISBN 1402071418
    Sprache: Englisch
    Fachgebiete: Technik
    RVK:
    RVK:
    Schlagwort(e): System-on-Chip ; Entwurf ; System-on-Chip ; Entwurf ; Electronic books.
    URL: Volltext  (Deutschlandweit zugänglich)
    URL: Cover
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 3
    Online-Ressource
    Online-Ressource
    New York, New York :Kluwer Academic Publishers,
    UID:
    almafu_9958069780102883
    Umfang: 1 online resource (312 p.)
    Ausgabe: Third edition.
    ISBN: 0-306-47640-1
    Inhalt: Features of the Third Edition: UP TO DATE STATE OF THE ART REUSE AS A SOLUTION FOR CIRCUIT DESIGNERS A CHRONICLE OF "BEST PRACTICES" ALL CHAPTERS UPDATED AND REVISED GENERIC GUIDELINES-NON TOOL SPECIFIC EMPHASIS ON HARD IP AND PHYSICAL DESIGN Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips. In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality. From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques.
    Anmerkung: Description based upon print version of record. , The System-on-Chip Design Process -- System-Level Design Issues: Rules and Tools -- The Macro Design Process -- RTL Coding Guidelines -- Macro Synthesis Guidelines -- Macro Verification Guidelines -- Developing Hard Macros -- Macro Deployment: Packaging for Reuse -- System Integration with Reusable Macros -- System-Level Verification Issues -- Data and Project Management -- Implementing Reuse-Based SoC Designs. , English
    Weitere Ausg.: ISBN 1-4020-7141-8
    Sprache: Englisch
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 4
    Online-Ressource
    Online-Ressource
    Boston, MA : Springer US
    UID:
    b3kat_BV045148500
    Umfang: 1 Online-Ressource (XX, 292 p)
    Ausgabe: 3
    ISBN: 9780306476402
    Inhalt: Features of the Third Edition: UP TO DATE STATE OF THE ART REUSE AS A SOLUTION FOR CIRCUIT DESIGNERS A CHRONICLE OF "BEST PRACTICES" ALL CHAPTERS UPDATED AND REVISED GENERIC GUIDELINES-NON TOOL SPECIFIC EMPHASIS ON HARD IP AND PHYSICAL DESIGN Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come.
    Inhalt: Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips. In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality.
    Inhalt: From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe ISBN 9781402071416
    Sprache: Englisch
    Fachgebiete: Technik
    RVK:
    Schlagwort(e): System-on-Chip ; Entwurf ; VHDL ; Softwarewiederverwendung
    URL: Volltext  (URL des Erstveröffentlichers)
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 5
    Online-Ressource
    Online-Ressource
    Boston [u.a.] : Kluwer Academic Publishers
    UID:
    gbv_524976805
    Umfang: Online-Ressource
    Ausgabe: 3rd ed.
    Ausgabe: Reproduktion Springer-11645
    Ausgabe: Springer eBook Collection. Computer Science
    ISBN: 9780306476402
    Inhalt: The System-on-Chip Design Process -- System-Level Design Issues: Rules and Tools -- The Macro Design Process -- RTL Coding Guidelines -- Macro Synthesis Guidelines -- Macro Verification Guidelines -- Developing Hard Macros -- Macro Deployment: Packaging for Reuse -- System Integration with Reusable Macros -- System-Level Verification Issues -- Data and Project Management -- Implementing Reuse-Based SoC Designs.
    Inhalt: Features of the Third Edition: UP TO DATE STATE OF THE ART REUSE AS A SOLUTION FOR CIRCUIT DESIGNERS A CHRONICLE OF "BEST PRACTICES" ALL CHAPTERS UPDATED AND REVISED GENERIC GUIDELINES-NON TOOL SPECIFIC EMPHASIS ON HARD IP AND PHYSICAL DESIGN Reuse Methodology Manual for System-on-a-Chip Designs, Third Edition outlines a set of best practices for creating reusable designs for use in a SoC design methodology. These practices are based on the authors' experience in developing reusable designs, as well as the experience of design teams in many companies around the world. Silicon and tool technologies move so quickly that many of the details of design-for-reuse will undoubtedly continue to evolve over time. But the fundamental aspects of the methodology described in this book have become widely adopted and are likely to form the foundation of chip design for some time to come. Development methodology necessarily differs between system designers and processor designers, as well as between DSP developers and chipset developers. However, there is a common set of problems facing everyone who is designing complex chips. In response to these problems, design teams have adopted a block-based design approach that emphasizes design reuse. Reusing macros (sometimes called "cores") that have already been designed and verified helps to address all of the problems above. However, in adopting reuse-based design, design teams have run into a significant problem. Reusing blocks that have not been explicitly designed for reuse has often provided little or no benefit to the team. The effort to integrate a pre-existing block into new designs can become prohibitively high, if the block does not provide the right views, the right documentation, and the right functionality. From this experience, design teams have realized that reuse-based design requires an explicit methodology for developing reusable macros that are easy to integrate into SoC designs. This manual focuses on describing these techniques.
    Weitere Ausg.: ISBN 9781402071416
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe ISBN 9781402071416
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe ISBN 9781475776096
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe ISBN 9780387740980
    Sprache: Englisch
    Fachgebiete: Technik
    RVK:
    Schlagwort(e): System-on-Chip ; Entwurf
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
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