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  • 1
    UID:
    almafu_9959186273102883
    Umfang: 1 online resource (VIII, 404 p.)
    Ausgabe: 1st ed. 1990.
    Ausgabe: Online edition Springer Lecture Notes Archive ; 041142-5
    ISBN: 0-387-34801-8
    Serie: Lecture Notes in Computer Science, 408
    Inhalt: Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States.
    Anmerkung: Bibliographic Level Mode of Issuance: Monograph , Design for verifiability -- Verification of synchronous circuits by symbolic logic simulation -- Constraints, abstraction, and verification -- Formalising the design of an SECD chip -- Reasoning about state machines in higher-order logic -- A mechanically derived systolic implementation of pyramid initialization -- Behavior-preserving transformations for high-level synthesis -- From programs to transistors: Verifying hardware synthesis tools -- Combining engineering vigor with mathematical rigor -- Totally verified systems: Linking verified software to verified hardware -- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components -- Complete trace structures -- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation -- Manipulating logical organization with system factorizations -- The verification of a bit-slice ALU -- Verification of a pipelined microprocessor using clio -- Verification of combinational logic in Nuprl -- Veritas+: A specification language based on type theory -- Categories for the working hardware designer. , English
    In: Springer eBooks
    Weitere Ausg.: ISBN 0-387-97226-9
    Sprache: Englisch
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 2
    UID:
    gbv_595129188
    Umfang: Online-Ressource (VI, 402 S.)
    Ausgabe: Online-Ausg. New York [u.a.] Springer 2006 Springer lecture notes archive
    ISBN: 9780387348018
    Serie: Lecture notes in computer science 408
    Inhalt: Design for verifiability -- Verification of synchronous circuits by symbolic logic simulation -- Constraints, abstraction, and verification -- Formalising the design of an SECD chip -- Reasoning about state machines in higher-order logic -- A mechanically derived systolic implementation of pyramid initialization -- Behavior-preserving transformations for high-level synthesis -- From programs to transistors: Verifying hardware synthesis tools -- Combining engineering vigor with mathematical rigor -- Totally verified systems: Linking verified software to verified hardware -- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components -- Complete trace structures -- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation -- Manipulating logical organization with system factorizations -- The verification of a bit-slice ALU -- Verification of a pipelined microprocessor using clio -- Verification of combinational logic in Nuprl -- Veritas+: A specification language based on type theory -- Categories for the working hardware designer.
    Inhalt: Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States.
    Anmerkung: Literaturangaben
    Weitere Ausg.: ISBN 0387972269
    Weitere Ausg.: ISBN 3540972269
    Weitere Ausg.: ISBN 9780387972268
    Weitere Ausg.: ISBN 9783540972266
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe Hardware specification, verification and synthesis Berlin : Springer, 1990 ISBN 0387972269
    Weitere Ausg.: ISBN 3540972269
    Sprache: Englisch
    Fachgebiete: Informatik
    RVK:
    Schlagwort(e): Hardware ; Spezifikation ; Hardwareverifikation ; Hardware ; Chemische Synthese ; Konferenzschrift
    URL: Volltext  (lizenzpflichtig)
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 3
    UID:
    gbv_025343521
    Umfang: VI, 402 S. , graph. Darst.
    ISBN: 0387972269 , 3540972269
    Serie: Lecture notes in computer science 408
    Anmerkung: Literaturangaben
    Weitere Ausg.: Online-Ausg. Hardware specification, verification and synthesis Berlin [u.a.] : Springer, 1990 ISBN 9780387348018
    Weitere Ausg.: Erscheint auch als Online-Ausgabe Leeser, Miriam Hardware Specification, Verification and Synthesis: Mathematical Aspects New York, NY : Springer New York, 1990 ISBN 9780387348018
    Sprache: Englisch
    Fachgebiete: Informatik
    RVK:
    Schlagwort(e): Hardware ; Spezifikation ; Hardwareverifikation ; Hardware ; Chemische Synthese ; Hardware ; Spezifikation ; Hardwareverifikation ; Hardware ; Chemische Synthese ; Konferenzschrift
    URL: Cover
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 4
    UID:
    almahu_9947921007902882
    Umfang: VIII, 404 p. , online resource.
    ISBN: 9780387348018
    Serie: Lecture Notes in Computer Science, 408
    Inhalt: Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States.
    Anmerkung: Design for verifiability -- Verification of synchronous circuits by symbolic logic simulation -- Constraints, abstraction, and verification -- Formalising the design of an SECD chip -- Reasoning about state machines in higher-order logic -- A mechanically derived systolic implementation of pyramid initialization -- Behavior-preserving transformations for high-level synthesis -- From programs to transistors: Verifying hardware synthesis tools -- Combining engineering vigor with mathematical rigor -- Totally verified systems: Linking verified software to verified hardware -- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components -- Complete trace structures -- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation -- Manipulating logical organization with system factorizations -- The verification of a bit-slice ALU -- Verification of a pipelined microprocessor using clio -- Verification of combinational logic in Nuprl -- Veritas+: A specification language based on type theory -- Categories for the working hardware designer.
    In: Springer eBooks
    Weitere Ausg.: Printed edition: ISBN 9780387972268
    Sprache: Englisch
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 5
    UID:
    almahu_9948621134302882
    Umfang: VIII, 404 p. , online resource.
    Ausgabe: 1st ed. 1990.
    ISBN: 9780387348018
    Serie: Lecture Notes in Computer Science, 408
    Inhalt: Current research into formal methods for hardware design is presented in the papers in this volume. Because of the complexity of VLSI circuits, assuring design validity before circuits are manufactured is imperative. The goal of research in this area is to develop methods of improving the design process and the quality of the resulting designs. The major trend apparent at the workshop is that researchers are rapidly moving away from post hoc proof techniques with their great expense. A number of papers were presented that dealt with problems of synthesizing correct circuits and of designing with the goal of verification. Researchers are also beginning to deal with the theoretical issues of reasoning about concurrent systems and asynchronous systems, and to introduce new logical tools such as constructive type theory and category theory. Most of the research reported was performed in the United States.
    Anmerkung: Design for verifiability -- Verification of synchronous circuits by symbolic logic simulation -- Constraints, abstraction, and verification -- Formalising the design of an SECD chip -- Reasoning about state machines in higher-order logic -- A mechanically derived systolic implementation of pyramid initialization -- Behavior-preserving transformations for high-level synthesis -- From programs to transistors: Verifying hardware synthesis tools -- Combining engineering vigor with mathematical rigor -- Totally verified systems: Linking verified software to verified hardware -- What's in a timing discipline? Considerations in the specification and synthesis of systems with interacting asynchronous and synchronous components -- Complete trace structures -- The design of a delay-insensitive microprocessor: An example of circuit synthesis by program transformation -- Manipulating logical organization with system factorizations -- The verification of a bit-slice ALU -- Verification of a pipelined microprocessor using clio -- Verification of combinational logic in Nuprl -- Veritas+: A specification language based on type theory -- Categories for the working hardware designer.
    In: Springer Nature eBook
    Weitere Ausg.: Printed edition: ISBN 9781475789287
    Weitere Ausg.: Printed edition: ISBN 9780387972268
    Sprache: Englisch
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 6
    UID:
    gbv_1649186231
    Umfang: Online-Ressource
    ISBN: 9780387348018
    Serie: Lecture Notes in Computer Science 408
    Weitere Ausg.: ISBN 9780387972268
    Weitere Ausg.: Buchausg. u.d.T. Hardware specification, verification and synthesis Berlin : Springer, 1990 ISBN 0387972269
    Weitere Ausg.: ISBN 3540972269
    Sprache: Englisch
    Fachgebiete: Informatik
    RVK:
    Schlagwort(e): Hardware ; Spezifikation ; Hardwareverifikation ; Hardware ; Chemische Synthese ; Konferenzschrift
    URL: Cover
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
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