UID:
almahu_9948352076602882
Umfang:
XV, 628 p. 1 illus.
,
online resource.
Ausgabe:
1st ed. 2020.
ISBN:
9783030432430
Serie:
Theoretical Computer Science and General Issues ; 9999
Inhalt:
This work is building on results from the book named "A Pipelined Multi-core MIPS Machine: Hardware Implementation and Correctness" by M. Kovalev, S.M. Müller, and W.J. Paul, published as LNCS 9000 in 2014. It presents, at the gate level, construction and correctness proof of a multi-core machine with pipelined processors and extensive operating system support with the following features: • MIPS instruction set architecture (ISA) for application and for system programming • cache coherent memory system • store buffers in front of the data caches • interrupts and exceptions • memory management units (MMUs) • pipelined processors: the classical five-stage pipeline is extended by two pipeline stages for address translation • local interrupt controller (ICs) supporting inter-processor interrupts (IPIs) • I/O-interrupt controller and a disk .
Anmerkung:
Introductory material -- on hierarchical hardware design -- hardware library -- basic processor design -- pipelining -- cache memory systems -- interrupt mechanism -- self modification, instruction buffer and nondeterministic ISA -- memory management units -- store buffers -- multi-core processors -- advanced programmable interrupt controllers (APICs) -- adding a disk -- I/O apic.
In:
Springer eBooks
Weitere Ausg.:
Printed edition: ISBN 9783030432423
Weitere Ausg.:
Printed edition: ISBN 9783030432447
Sprache:
Englisch
Fachgebiete:
Informatik
DOI:
10.1007/978-3-030-43243-0
URL:
https://doi.org/10.1007/978-3-030-43243-0
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