UID:
almahu_9949419790002882
Format:
XII, 583 p. 215 illus., 211 illus. in color.
,
online resource.
Edition:
1st ed. 2022.
ISBN:
9783031130748
Content:
This book serves as a single-source reference to key machine learning (ML) applications and methods in digital and analog design and verification. Experts from academia and industry cover a wide range of the latest research on ML applications in electronic design automation (EDA), including analysis and optimization of digital design, analysis and optimization of analog design, as well as functional verification, FPGA and system level designs, design for manufacturing (DFM), and design space exploration. The authors also cover key ML methods such as classical ML, deep learning models such as convolutional neural networks (CNNs), graph neural networks (GNNs), generative adversarial networks (GANs) and optimization methods such as reinforcement learning (RL) and Bayesian optimization (BO). All of these topics are valuable to chip designers and EDA developers and researchers working in digital and analog designs and verification. Serves as a single-source reference to key machine learning (ML) applications and methods in digital and analog design and verification; Covers classical ML methods, as well as deep learning models such as convolutional neural networks (CNNs), graph neural networks (GNNs), generative adversarial networks (GANs) and optimization methods such as reinforcement learning (RL) and Bayesian optimization (BO); Discusses machine learning ML's applications in electronic design automation (EDA), especially in the design automation of VLSI integrated circuits.
Note:
Introduction -- Analysis of Digital Design: Routability Optimization for Industrial Designs at Sub-14nm Process Nodes Using Machine Learning -- RouteNet: Routability Prediction for Mixed-size Designs Using Convolutional Neural Network -- High Performance Graph Convolutional networks with Applications in Testability Analysis -- MAVIREC: ML-Aided Vectored IR-Drop Estimation and Classification -- GRANNITE: Graph Neural Network Inference for Transferable Power Estimation -- Machine Learning-Enabled High-Frequency Low-Power Digital Design Implementation at Advanced Process Nodes -- Optimization of Digital Design: Chip Placement with Deep Reinforcement learning -- DREAMPlace: Deep Learning Toolkit-Enabled GPU Acceleration for Modern VLSI Placement -- TreeNet: Deep Point Cloud Embedding for Routing Tree Construction -- Asynchronous Reinforcement Learning Framework for Net Order Exploration in Detailed Routing -- Standard Cell Routing with Reinforcement Learning and Genetic Algorithm in Advanced Technology Nodes -- PrefixRL: Optimization of Parallel Prefix Circuits using Deep Reinforcement Learning -- GAN-CTS: A Generative Adversarial Framework for Clock Tree Prediction and Optimization -- Analysis and Optimization of Analog Design: Machine Learning Techniques in Analog Layout Automation -- Layout Symmetry Annotation for Analog Circuits with Graph Neural Networks -- ParaGraph: Layout parasitics and device parameter prediction using graph neural network -- GCN-RL circuit designer: Transferable transistor sizing with graph neural networks and reinforcement learn -- Parasitic-Aware Analog Circuit Sizing with Graph Neural Networks and Bayesian Optimization -- Logic and Physical Verification: Deep Predictive Coverage Collection/ Dynamically Optimized Test Generation Using Machine Learning -- Novelty-Driven Verification: Using Machine Learning to Identify Novel Stimuli and Close Coverage -- Using Machine Learning Clustering To Find Large Coverage Holes -- GAN-OPC: Mask optimization with lithography-guided generative adversarial nets -- Layout hotspot detection with feature tensor generation and deep biased learning.
In:
Springer Nature eBook
Additional Edition:
Printed edition: ISBN 9783031130731
Additional Edition:
Printed edition: ISBN 9783031130755
Additional Edition:
Printed edition: ISBN 9783031130762
Language:
English
DOI:
10.1007/978-3-031-13074-8
URL:
https://doi.org/10.1007/978-3-031-13074-8
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