Kooperativer Bibliotheksverbund

UID:

Format: XII, 432 p. , online resource.

ISBN: 9783540397243

Series Statement: Lecture Notes in Computer Science, 2860

Note: Invited Talks -- What Is beyond the RTL Horizon for Microprocessor and System Design? -- The Charme of Abstract Entities -- Tutorial -- The PSL/Sugar Specification Language A Language for all Seasons -- Software Verification -- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular -- Predicate Abstraction with Minimum Predicates -- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning -- Processor Verification -- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP -- A Hazards-Based Correctness Statement for Pipelined Circuits -- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT -- Automata Based Methods -- On Complementing Nondeterministic Büchi Automata -- Coverage Metrics for Formal Verification -- “More Deterministic” vs. “Smaller” Büchi Automata for Efficient LTL Model Checking -- Short Papers 1 -- An Optimized Symbolic Bounded Model Checking Engine -- Constrained Symbolic Simulation with Mathematica and ACL2 -- Semi-formal Verification of Memory Systems by Symbolic Simulation -- CTL May Be Ambiguous When Model Checking Moore Machines -- Specification Methods -- Reasoning about GSTE Assertion Graphs -- Towards Diagrammability and Efficiency in Event Sequence Languages -- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving -- Protocol Verification -- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking -- On the Correctness of an Intrusion-Tolerant Group Communication Protocol -- Exact and Efficient Verification of Parameterized Cache Coherence Protocols -- Short Papers 2 -- Design and Implementation of an Abstract Interpreter for VHDL -- A Programming Language Based Analysis of Operand Forwarding -- Integrating RAM and Disk Based Verification within the Mur? Verifier -- Design and Verification of CoreConnectTM IP Using Esterel -- Theorem Proving -- Inductive Assertions and Operational Semantics -- A Compositional Theory of Refinement for Branching Time -- Linear and Nonlinear Arithmetic in ACL2 -- Bounded Model Checking -- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking -- Convergence Testing in Term-Level Bounded Model Checking -- The ROBDD Size of Simple CNF Formulas -- Model Checking and Application -- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems -- Finite Horizon Analysis of Markov Chains with the Mur? Verifier -- Improved Symbolic Verification Using Partitioning Techniques.

In: Springer eBooks

Additional Edition: Printed edition: ISBN 9783540203636

Language: English

Subjects: Computer Science

Keywords: Konferenzschrift

DOI: 10.1007/b93958

URL: http://dx.doi.org/10.1007/b93958

URL: lizenzpflichtig

URL: Volltext  (lizenzpflichtig)

URL: Inhaltstext

UID:

Format: XII, 432 p. , online resource.

Edition: 1st ed. 2003.

ISBN: 9783540397243

Series Statement: Lecture Notes in Computer Science, 2860

Note: Invited Talks -- What Is beyond the RTL Horizon for Microprocessor and System Design? -- The Charme of Abstract Entities -- Tutorial -- The PSL/Sugar Specification Language A Language for all Seasons -- Software Verification -- Finding Regularity: Describing and Analysing Circuits That Are Not Quite Regular -- Predicate Abstraction with Minimum Predicates -- Efficient Symbolic Model Checking of Software Using Partial Disjunctive Partitioning -- Processor Verification -- Instantiating Uninterpreted Functional Units and Memory System: Functional Verification of the VAMP -- A Hazards-Based Correctness Statement for Pipelined Circuits -- Analyzing the Intel Itanium Memory Ordering Rules Using Logic Programming and SAT -- Automata Based Methods -- On Complementing Nondeterministic Büchi Automata -- Coverage Metrics for Formal Verification -- "More Deterministic" vs. "Smaller" Büchi Automata for Efficient LTL Model Checking -- Short Papers 1 -- An Optimized Symbolic Bounded Model Checking Engine -- Constrained Symbolic Simulation with Mathematica and ACL2 -- Semi-formal Verification of Memory Systems by Symbolic Simulation -- CTL May Be Ambiguous When Model Checking Moore Machines -- Specification Methods -- Reasoning about GSTE Assertion Graphs -- Towards Diagrammability and Efficiency in Event Sequence Languages -- Executing the Formal Semantics of the Accellera Property Specification Language by Mechanised Theorem Proving -- Protocol Verification -- On Combining Symmetry Reduction and Symbolic Representation for Efficient Model Checking -- On the Correctness of an Intrusion-Tolerant Group Communication Protocol -- Exact and Efficient Verification of Parameterized Cache Coherence Protocols -- Short Papers 2 -- Design and Implementation of an Abstract Interpreter for VHDL -- A Programming Language Based Analysis of Operand Forwarding -- Integrating RAM and Disk Based Verification within the Mur? Verifier -- Design and Verification of CoreConnectTM IP Using Esterel -- Theorem Proving -- Inductive Assertions and Operational Semantics -- A Compositional Theory of Refinement for Branching Time -- Linear and Nonlinear Arithmetic in ACL2 -- Bounded Model Checking -- Efficient Distributed SAT and SAT-Based Distributed Bounded Model Checking -- Convergence Testing in Term-Level Bounded Model Checking -- The ROBDD Size of Simple CNF Formulas -- Model Checking and Application -- Efficient Hybrid Reachability Analysis for Asynchronous Concurrent Systems -- Finite Horizon Analysis of Markov Chains with the Mur? Verifier -- Improved Symbolic Verification Using Partitioning Techniques.

In: Springer Nature eBook

Additional Edition: Printed edition: ISBN 9783662163191

Additional Edition: Printed edition: ISBN 9783540203636

Language: English

DOI: 10.1007/b93958

URL: https://doi.org/10.1007/b93958

UID:

Format: XII, 426 S. , graph. Darst.

ISBN: 354020363X

Series Statement: Lecture notes in computer science 2860

Note: Literaturangaben

Additional Edition: Erscheint auch als Online-Ausgabe Geist, Daniel Correct Hardware Design and Verification Methods Berlin, Heidelberg : Springer Berlin Heidelberg, 2003 ISBN 9783540203636

Language: English

Subjects: Computer Science

Keywords: Hardwareentwurf ; Formale Methode ; Hardwareverifikation ; Formale Methode ; Model Checking ; System-on-Chip ; Entwurfsautomation ; Formale Methode ; Entwurfssprache ; Konferenzschrift

URL: Inhaltsverzeichnis

URL: Cover

URL: Inhaltstext

URL: http://www.loc.gov/catdir/enhancements/fy0818/2003057017-d.html

UID:

Format: XII, 426 Seiten , graph. Darst. , 24 cm

ISBN: 354020363X

Series Statement: Lecture notes in computer science 2860

Note: Literaturangaben , Text engl.

Language: English

Keywords: Hardwareentwurf ; Formale Methode ; Kongress ; L'Aquila 〈2003〉 ; Hardwareverifikation ; Formale Methode ; Kongress ; L'Aquila 〈2003〉 ; Model Checking ; Kongress ; L'Aquila 〈2003〉 ; System-on-Chip ; Entwurfsautomation ; Formale Methode ; Kongress ; L'Aquila 〈2003〉 ; Entwurfssprache ; Kongress ; L'Aquila 〈2003〉 ; Kongress ; Konferenzschrift