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  • 1
    Online Resource
    Online Resource
    Berlin, Heidelberg :Springer Berlin Heidelberg,
    UID:
    almahu_9947920522402882
    Format: XVI, 196 p. , online resource.
    ISBN: 9783540246572
    Series Statement: Lecture Notes in Computer Science, 2963
    Content: In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.
    Note: 1. Introduction -- 1. Introduction -- 2. Related Work -- 3. The SAFL Language -- 4. Soft Scheduling -- 5. High-Level Synthesis of SAFL -- 6. Analysis and Optimisation of Intermediate Code -- 7. Dealing with I/O -- 8. Combining Behaviour and Structure -- 9. Transformation of SAFL Specifications -- 10. Case Study -- 11. Conclusions and Further Work.
    In: Springer eBooks
    Additional Edition: Printed edition: ISBN 9783540213062
    Language: English
    Subjects: Computer Science
    RVK:
    URL: Volltext  (lizenzpflichtig)
    Library Location Call Number Volume/Issue/Year Availability
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  • 2
    UID:
    gbv_382966325
    Format: XVI, 195 S. , Ill., graph. Darst. , 24 cm
    ISBN: 3540213066
    Series Statement: Lecture notes in computer science 2963
    Note: Zugl. revised version of: Cambridge, Univ., Diss., 2003
    Additional Edition: Erscheint auch als Online-Ausgabe Sharp, Richard Higher-Level Hardware Synthesis Berlin, Heidelberg : Springer Berlin Heidelberg, 2004 ISBN 9783540213062
    Language: English
    Subjects: Computer Science
    RVK:
    Keywords: Hardwareentwurf ; Logiksynthese ; Hardwarebeschreibungssprache ; Hardwareverifikation ; Einführung ; Hochschulschrift
    URL: Cover
    Library Location Call Number Volume/Issue/Year Availability
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  • 3
    Online Resource
    Online Resource
    Berlin, Heidelberg :Springer Berlin Heidelberg :
    UID:
    almahu_9948621554602882
    Format: XVI, 196 p. , online resource.
    Edition: 1st ed. 2004.
    ISBN: 9783540246572
    Series Statement: Lecture Notes in Computer Science, 2963
    Content: In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its "unrealistic optimism," Moore's prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore's law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.
    Note: 1. Introduction -- 1. Introduction -- 2. Related Work -- 3. The SAFL Language -- 4. Soft Scheduling -- 5. High-Level Synthesis of SAFL -- 6. Analysis and Optimisation of Intermediate Code -- 7. Dealing with I/O -- 8. Combining Behaviour and Structure -- 9. Transformation of SAFL Specifications -- 10. Case Study -- 11. Conclusions and Further Work.
    In: Springer Nature eBook
    Additional Edition: Printed edition: ISBN 9783662197103
    Additional Edition: Printed edition: ISBN 9783540213062
    Language: English
    Library Location Call Number Volume/Issue/Year Availability
    BibTip Others were also interested in ...
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