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  • 1
    UID:
    gbv_397626282
    Umfang: XII, 506 S. , graph. Darst. , 235 mm x 155 mm
    ISBN: 3540236104
    Serie: Lecture notes in computer science 3299
    Anmerkung: Literaturangaben
    Weitere Ausg.: Erscheint auch als Online-Ausgabe Wang, Farn Automated Technology for Verification and Analysis Berlin, Heidelberg : Springer Berlin Heidelberg, 2004 ISBN 9783540236108
    Sprache: Englisch
    Fachgebiete: Informatik
    RVK:
    Schlagwort(e): Systementwurf ; Formale Methode ; Verifikation ; Formale Methode ; Verifikation ; Model Checking ; Softwareentwicklung ; Hardwareentwurf ; Verifikation ; Model Checking ; Entwurfsautomation ; Model Checking ; Konferenzschrift ; Kongress ; Konferenzschrift
    URL: Cover
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 2
    UID:
    almahu_9947920705202882
    Umfang: XII, 510 p. , online resource.
    ISBN: 9783540304760
    Serie: Lecture Notes in Computer Science, 3299
    Anmerkung: Keynote Speech -- Games for Formal Design and Verification of Reactive Systems -- Evolution of Model Checking into the EDA Industry -- Abstraction Refinement -- Invited Speech -- Tools for Automated Verification of Web Services -- Theorem Proving Languages for Verification -- An Automated Rigorous Review Method for Verifying and Validating Formal Specifications -- Papers -- Toward Unbounded Model Checking for Region Automata -- Search Space Partition and Case Basis Exploration for Reducing Model Checking Complexity -- Synthesising Attacks on Cryptographic Protocols -- Büchi Complementation Made Tighter -- SAT-Based Verification of Safe Petri Nets -- Disjunctive Invariants for Numerical Systems -- Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas -- Fair Testing Revisited: A Process-Algebraic Characterisation of Conflicts -- Exploiting Symmetries for Testing Equivalence in the Spi Calculus -- Using Block-Local Atomicity to Detect Stale-Value Concurrency Errors -- Abstraction-Based Model Checking Using Heuristical Refinement -- A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata -- Design and Evaluation of a Symbolic and Abstraction-Based Model Checker -- Component-Wise Instruction-Cache Behavior Prediction -- Validating the Translation of an Industrial Optimizing Compiler -- Composition of Accelerations to Verify Infinite Heterogeneous Systems -- Hybrid System Verification Is Not a Sinecure -- Providing Automated Verification in HOL Using MDGs -- Specification, Abduction, and Proof -- Introducing Structural Dynamic Changes in Petri Nets: Marked-Controlled Reconfigurable Nets -- Typeness for ?-Regular Automata -- Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits -- Mutation Coverage Estimation for Model Checking -- Modular Model Checking of Software Specifications with Simultaneous Environment Generation -- Rabin Tree and Its Application to Group Key Distribution -- Using Overlay Networks to Improve VoIP Reliability -- Integrity-Enhanced Verification Scheme for Software-Intensive Organizations -- RCGES: Retargetable Code Generation for Embedded Systems -- Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets -- First-Order LTL Model Checking Using MDGs -- Localizing Errors in Counterexample with Iteratively Witness Searching -- Verification of WCDMA Protocols and Implementation -- Efficient Representation of Algebraic Expressions -- Development of RTOS for PLC Using Formal Methods -- Reducing Parametric Automata: A Multimedia Protocol Service Case Study -- Synthesis of State Feedback Controllers for Parameterized Discrete Event Systems -- Solving Box-Pushing Games via Model Checking with Optimizations -- CLP Based Static Property Checking -- A Temporal Assertion Extension to Verilog.
    In: Springer eBooks
    Weitere Ausg.: Printed edition: ISBN 9783540236108
    Sprache: Englisch
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
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  • 3
    UID:
    gbv_749111283
    Umfang: Online-Ressource (XII, 506 p. Also available online) , digital
    Ausgabe: Springer eBook Collection. Computer Science
    ISBN: 9783540304760 , 3540236104 , 9783540236108
    Serie: Lecture Notes in Computer Science 3299
    Inhalt: This book constitutes the refereed proceedings of the Second International Conference on Automated Technology for Verificaton and Analysis, ATVA 2004, held in Taipei, Taiwan in October/November 2004. The 24 revised full papers presented together with abstracts of 6 invited presentations and 7 special track papers were carefully reviewed and selected from 69 submissions. Among the topics addressed are model-checking theory, theorem-proving theory, state-space reduction techniques, languages in automated verification, parametric analysis, optimization, formal performance analysis, real-time systems, embedded systems, infinite-state systems, Petri nets, UML, synthesis, and tools
    Weitere Ausg.: ISBN 9783540236108
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe ISBN 9783540236108
    Weitere Ausg.: Erscheint auch als Druck-Ausgabe ISBN 9783662191248
    Sprache: Englisch
    Fachgebiete: Informatik
    RVK:
    URL: Volltext  (lizenzpflichtig)
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
  • 4
    UID:
    almahu_9948621695502882
    Umfang: XII, 510 p. , online resource.
    Ausgabe: 1st ed. 2004.
    ISBN: 9783540304760
    Serie: Lecture Notes in Computer Science, 3299
    Anmerkung: Keynote Speech -- Games for Formal Design and Verification of Reactive Systems -- Evolution of Model Checking into the EDA Industry -- Abstraction Refinement -- Invited Speech -- Tools for Automated Verification of Web Services -- Theorem Proving Languages for Verification -- An Automated Rigorous Review Method for Verifying and Validating Formal Specifications -- Papers -- Toward Unbounded Model Checking for Region Automata -- Search Space Partition and Case Basis Exploration for Reducing Model Checking Complexity -- Synthesising Attacks on Cryptographic Protocols -- Büchi Complementation Made Tighter -- SAT-Based Verification of Safe Petri Nets -- Disjunctive Invariants for Numerical Systems -- Validity Checking for Quantifier-Free First-Order Logic with Equality Using Substitution of Boolean Formulas -- Fair Testing Revisited: A Process-Algebraic Characterisation of Conflicts -- Exploiting Symmetries for Testing Equivalence in the Spi Calculus -- Using Block-Local Atomicity to Detect Stale-Value Concurrency Errors -- Abstraction-Based Model Checking Using Heuristical Refinement -- A Global Timed Bisimulation Preserving Abstraction for Parametric Time-Interval Automata -- Design and Evaluation of a Symbolic and Abstraction-Based Model Checker -- Component-Wise Instruction-Cache Behavior Prediction -- Validating the Translation of an Industrial Optimizing Compiler -- Composition of Accelerations to Verify Infinite Heterogeneous Systems -- Hybrid System Verification Is Not a Sinecure -- Providing Automated Verification in HOL Using MDGs -- Specification, Abduction, and Proof -- Introducing Structural Dynamic Changes in Petri Nets: Marked-Controlled Reconfigurable Nets -- Typeness for ?-Regular Automata -- Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits -- Mutation Coverage Estimation for Model Checking -- Modular Model Checking of Software Specifications with Simultaneous Environment Generation -- Rabin Tree and Its Application to Group Key Distribution -- Using Overlay Networks to Improve VoIP Reliability -- Integrity-Enhanced Verification Scheme for Software-Intensive Organizations -- RCGES: Retargetable Code Generation for Embedded Systems -- Verification of Analog and Mixed-Signal Circuits Using Timed Hybrid Petri Nets -- First-Order LTL Model Checking Using MDGs -- Localizing Errors in Counterexample with Iteratively Witness Searching -- Verification of WCDMA Protocols and Implementation -- Efficient Representation of Algebraic Expressions -- Development of RTOS for PLC Using Formal Methods -- Reducing Parametric Automata: A Multimedia Protocol Service Case Study -- Synthesis of State Feedback Controllers for Parameterized Discrete Event Systems -- Solving Box-Pushing Games via Model Checking with Optimizations -- CLP Based Static Property Checking -- A Temporal Assertion Extension to Verilog.
    In: Springer Nature eBook
    Weitere Ausg.: Printed edition: ISBN 9783540236108
    Weitere Ausg.: Printed edition: ISBN 9783662191248
    Sprache: Englisch
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
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