In:
Electrical Engineering in Japan, Wiley, Vol. 175, No. 4 ( 2011-06), p. 48-56
Abstract:
One‐bit signal processing based on delta‐sigma modulation has been studied for hardware implementation of signal processing systems. In the 1‐bit signal processing, finite word‐length problems such as overflow and coefficient quantization error occur. To solve the problems, a new design method with state space is proposed in this paper. Digital filters are designed to show the feasibility of the method. First, the L 1 / L 2 ‐sensitivity is shown to evaluate coefficient quantization error and L 2 scaling constraints to prevent overflow. Second, a state space equation is presented and the L 1 / L 2 ‐sensitivity and L 2 ‐scaling constraints are extended to take the filter structure and oversampling effects into account. Finally, the proposed method is shown to attain a higher SNR than conventional ones. © 2011 Wiley Periodicals, Inc. Electr Eng Jpn, 175(4): 48–56, 2011; Published online in Wiley Online Library ( wileyonlinelibrary.com ). DOI 10.1002/eej.21075
Type of Medium:
Online Resource
ISSN:
0424-7760
,
1520-6416
Language:
English
Publisher:
Wiley
Publication Date:
2011
detail.hit.zdb_id:
1480222-3
