In:
SID Symposium Digest of Technical Papers, Wiley, Vol. 48, No. 1 ( 2017-05), p. 68-71
Abstract:
In this paper, high reliable a‐IGZO TFT gate driving circuit was
designed. Series‐connected two‐transistor (STT) structure and dual low‐voltage‐level power signal (Vss) were used to solve the
initial negative Vth of IGZO TFTs. Special pull‐down holding part was designed for wider Vth shift window during panel operation.
The Vth shift margin of this proposed GOA design is from ‐5V to +9V by using Eldo‐Spice simulation system. In addition, the pull‐up
control part could also play a role to pull the Q node voltage down and it is helpful for narrow border design. Finally, a 31‐in.
8K4K 287‐ppi TFT‐LCD was successfully demonstrated based on the study above.
Type of Medium:
Online Resource
ISSN:
0097-966X
,
2168-0159
DOI:
10.1002/sdtp.2017.48.issue-1
Language:
English
Publisher:
Wiley
Publication Date:
2017
detail.hit.zdb_id:
2526337-7