In:
Nature Communications, Springer Science and Business Media LLC, Vol. 14, No. 1 ( 2023-06-23)
Kurzfassung:
A new type of heterojunction non-volatile memory transistor (H-MTR) has been developed, in which the negative transconductance (NTC) characteristics can be controlled systematically by a drain-aligned floating gate. In the H-MTR, a reliable transition between N-shaped transfer curves with distinct NTC and monolithically current-increasing transfer curves without apparent NTC can be accomplished through programming operation. Based on the H-MTR, a binary/ternary reconfigurable logic inverter (R-inverter) has been successfully implemented, which showed an unprecedentedly high static noise margin of 85% for binary logic operation and 59% for ternary logic operation, as well as long-term stability and outstanding cycle endurance. Furthermore, a ternary/binary dynamic logic conversion-in-memory has been demonstrated using a serially-connected R-inverter chain. The ternary/binary dynamic logic conversion-in-memory could generate three different output logic sequences for the same input signal in three logic levels, which is a new logic computing method that has never been presented before.
Materialart:
Online-Ressource
ISSN:
2041-1723
DOI:
10.1038/s41467-023-39394-5
Sprache:
Englisch
Verlag:
Springer Science and Business Media LLC
Publikationsdatum:
2023
ZDB Id:
2553671-0
