In:
Chinese Physics B, IOP Publishing, Vol. 28, No. 10 ( 2019-09-01), p. 106802-
Abstract:
We present a new charge trapping memory (CTM) device with the Au/Ga 2 O 3 /SiO 2 /Si structure, which is fabricated by using the magnetron sputtering, high-temperature annealing, and vacuum evaporation techniques. Transmission electron microscopy diagrams show that the thickness of the SiO 2 tunneling layer can be controlled by the annealing temperature. When the devices are annealed at 760 °C, the measured C – V hysteresis curves exhibit a maximum 6 V memory window under a ±13 V sweeping voltage. In addition, a slight degradation of the device voltage and capacitance indicates the robust retention properties of flat-band voltage and high/low state capacitance. These distinctive advantages are attributed to oxygen vacancies and inter-diffusion layers, which play a critical role in the charge trapping process.
Type of Medium:
Online Resource
ISSN:
1674-1056
DOI:
10.1088/1674-1056/ab3e62
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2019
detail.hit.zdb_id:
2412147-2