In:
COMPEL: The International Journal for Computation and Mathematics in Electrical and Electronic Engineering, Emerald, Vol. 33, No. 6 ( 2014-10-28), p. 2121-2138
Abstract:
– The purpose of this paper is to provide a new three dimension physically based model to calculate the initial stress in silicon germanium (SiGe) film due to thermal mismatch after deposition. We should note that there are many other sources of initial stress in SiGe films or in the substrate. Here, the author is focussing only on how to model the initial stress arising from thermal mismatch in SiGe film. The author uses this initial stress to calculate numerically the resulting extrinsic stress distribution in a nanoscale PMOS transistor. This extrinsic stress is used by industrials and manufacturers as Intel or IBM to boost the performances of the nanoscale PMOS and NMOS transistors. It is now admitted that compressive stress enhances the mobility of holes and tensile stress enhances the mobility of electrons in the channel. Design/methodology/approach – During thermal processing, thin film materials like polysilicon, silicon nitride, silicon dioxide, or SiGe expand or contract at different rates compared to the silicon substrate according to their thermal expansion coefficients. The author defines the thermal expansion coefficient as the rate of change of strain with respect to temperature. Findings – Several numerical experiments have been used for different temperatures ranging from 30 to 1,000°C. These experiments did show that the temperature affects strongly the extrinsic stress in the channel of a 45 nm PMOS transistor. On the other hand, the author has compared the extrinsic stress due to lattice mismatch with the extrinsic stress due to thermal mismatch. The author found that these two types of stress have the same order (see the numerical results on Figures 4 and 12). And, these are great findings for semiconductor industry. Practical implications – Front-end process induced extrinsic stress is used by manufacturers of nanoscale transistors as the new scaling vector for the 90 nm node technology and below. The extrinsic stress has the advantage of improving the performances of PMOSFETs and NMOSFETs transistors by enhancing mobility. This mobility enhancement fundamentally results from alteration of electronic band structure of silicon due to extrinsic stress. Then, the results are of great importance to manufacturers and industrials. The evidence is that these results show that the extrinsic stress in the channel depends also on the thermal mismatch between materials and not only on the material mismatch. Originality/value – The model the author is proposing to calculate the initial stress due to thermal mismatch is novel and original. The author validated the values of the initial stress with those obtained by experiments in Al-Bayati et al. (2005). Using the uniaxial stress generation technique of Intel (see Figure 2). Al-Bayati et al. (2005) found experimentally that for 17 percent germanium concentration, a compressive initial stress of 1.4 GPa is generated inside the SiGe layer.
Type of Medium:
Online Resource
ISSN:
0332-1649
DOI:
10.1108/COMPEL-11-2013-0390
Language:
English
Publisher:
Emerald
Publication Date:
2014
detail.hit.zdb_id:
1501321-2
