In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 35, No. 9R ( 1996-09-01), p. 4618-
Abstract:
A simple and easily manufacturable shallow trench isolation (STI) process is developed for 1 Gbit dynamic random access memory (DRAM) and possibly DRAMs with ever greater capacity. The main features of this STI scheme are dual slope trench formation and selective dry-etching-assisted chemical mechanical polishing (CMP) planarization. The dual slope trench is formed by utilizing polymer generation during trench etching to improve the sub-threshold conduction characteristics (hump-free sub-threshold) and reduce the threshold voltage variation. The basic elements of dry-etching-assisted planarization are to locally form oxide mesas using a highly selective dry etching, and to minimize the amount of CMP simply by removing the locally formed oxide mesas. This new dry-etching-assisted CMP planarization significantly reduces dishing in the large field area and improves the flatness between the high and low pattern density areas such as the cell array and periphery region in a high-density DRAM.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.35.4618
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
1996
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
