In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 44, No. 5S ( 2005-05-01), p. 3436-
Abstract:
A new mixed analog/digital partial response maximum likelihood (PRML) architecture for the optical drive system is presented. To realize a high-speed, low-power and low-cost solution, new data and clock recovery circuits are proposed. The proposed architecture is based on the efficient combination of digital and analog circuits for providing high-speed and low-power data detection for optical data storage systems. The presented circuit shows increased operating speed by 67%, reduced power consumption by 28% and reduced area by 42%, therefore it provides a high-speed, low-power and low-cost system on chip solution for the future optical drive system. A test chip produced is fabricated using 0.18 µm CMOS technology and the product has been proved to demonstrate the performance of the proposed architecture.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.44.3436
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2005
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7