In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 44, No. 9L ( 2005-09-01), p. L1214-
Abstract:
Thanks to the combination of damascene gate and outer poly-Si sidewall spacer process, we have successfully fabricated twin silicon–oxide–nitride–oxide–silicon (SONOS) memory (TSM) transistors with 20-nm twin nitride storage nodes under an 80-nm gate. In terms of device manufacturability, the damascene gate process makes it possible to realize physically separated structure and the outer poly-Si sidewall spacer scheme contributes to realization of 20-nm long nitride storage node. Compared with conventional SONOS transistor, the fabricated TSM transistor maintains its threshold voltage margin between the forward and reverse reads down to 80-nm long gate. The TSM transistor also shows stable and reliable characteristics: up to 10 5 program/erase cycles endurance and fairly good bake retention at 150°C.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.44.L1214
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2005
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7