In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 49, No. 4S ( 2010-04-01), p. 04DC02-
Abstract:
In this work, we carry out an experimental validated three-dimensional “atomistic” device-circuit coupled simulation to study the discrete-dopant-induced power and delay fluctuations in 16-nm-gate complementary metal–oxide–semiconductor (CMOS) circuits. The equivalent gate oxide thicknesses (EOTs) of planar CMOS range from 1.2 nm to 0.2 nm. SiO 2 is used at gate oxide thicknesses of 1.2 and 0.8 nm, Al 2 O 3 at an EOT of 0.4 nm, and HfO 2 at an EOT of 0.2 nm. Under the same device threshold voltage, as EOT decreases from 1.2 to 0.2 nm, the fluctuations of threshold voltage and gate capacitance for CMOS transistors are reduced by 43 and 55%, respectively. For the state-of-art nanoscale circuits using high-dielectric constant (high-κ) materials, the delay time fluctuation is suppressed significantly from 0.1 to 0.03 ps. For the power characteristics, although the nominal powers of circuits using high-κ dielectrics are increased owing to the increased EOT, the fluctuations of dynamic power, short circuit power, and static power are reduced by 40, 70, and 30%, respectively.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.49.04DC02
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2010
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
