In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 49, No. 6S ( 2010-06-01), p. 06GG11-
Abstract:
The influences of source/drain extension region engineering and high- k gate dielectrics on the device performance of tri-gate body-tied fin field-effect transistors (FinFETs) was investigated to achieve the International Technology Roadmap for Semiconductor (ITRS) projections for high-performance (HP) logic technology. The impact of lateral source/drain doping gradient ( L dg ) and spacer length ( L sp ) on short-channel effects (SCEs) was extensively analyzed by three-dimensional device simulation. Results show that a lateral doping gradient along with an appropriate spacer length not only can effectively control SCEs, resulting in a low off-current, but also can be optimized to achieve low values of intrinsic gate delay and high values of on-current. The ratio of spacer length to lateral doping gradient ( L sp / L dg ) between 2.7 and 4 is optimal for achieving a low intrinsic gate delay, a low off-current, and a high on/off-current ratio. The present work provides valuable design guidelines in the performance of tri-gate body-tied FinFETs with optimal source/drain extension region engineering and serves as a tool for optimizing important device and technological parameters.
Type of Medium:
Online Resource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.49.06GG11
Language:
Unknown
Publisher:
IOP Publishing
Publication Date:
2010
detail.hit.zdb_id:
218223-3
detail.hit.zdb_id:
797294-5
detail.hit.zdb_id:
2006801-3
detail.hit.zdb_id:
797295-7
