In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 50, No. 8R ( 2011-08-01), p. 084301-
Kurzfassung:
This paper presents a three-dimensional (3D) simulation study of source/drain (S/D)-tied (SDT) double-gate (DG) fin field-effect transistor (FinFET) design for 16-nm half-pitch technology generation and beyond using technology computer-aided design (TCAD) tools. A simple process to fabricate the proposed SDT FinFET is proposed. An investigation of the fin width ( W fin ) on the electrical characteristics is shown, suggesting that a reduced W fin is good for both the suppression of short-channel effects and the reduction of parasitic capacitance in SDT FinFETs. Also, the self-heating can be well controlled in our proposed SDT FinFET which is a difficult task for SOI family. The proposed FinFET is also compared with the existing experimental data, showing that the SDT FinFET not only demonstrates desired short-channel characteristics due to its inherent structure advantages (partially insulating oxide under the channel region), but also reduces the costs of device fabrication due to its simple process method and planar-like structure.
Materialart:
Online-Ressource
ISSN:
0021-4922
,
1347-4065
DOI:
10.1143/JJAP.50.084301
Sprache:
Unbekannt
Verlag:
IOP Publishing
Publikationsdatum:
2011
ZDB Id:
218223-3
ZDB Id:
797294-5
ZDB Id:
2006801-3
ZDB Id:
797295-7
