In:
ACM SIGMICRO Newsletter, Association for Computing Machinery (ACM), Vol. 17, No. 4 ( 1986-12-21), p. 104-115
Abstract:
There are a growing number of micro-architectures that employ pipelined array units for high-speed floating point applications. To obtain the performance required in such applications, effective loop optimization is crucial. The loop optimization problem for micro-architectures with pipelined processing units is similar to the problem of array processor loop optimization. The URPR method has been proven to be an effective, low-complexity approach to optimizing loops in array processor programs, so we conducted a case study of the method applied to a representative pipelined microarchitecture based on the AMD29500 chip family. The results of applying two URPR compaction algorithms and a new compaction algorithm to the 29500-based micro-architecture are presented. With the new compaction algorithm, we were able to realize microcode as efficient as the complex microcode manually derived by AMD.
Type of Medium:
Online Resource
ISSN:
1050-916X
Language:
English
Publisher:
Association for Computing Machinery (ACM)
Publication Date:
1986
detail.hit.zdb_id:
243814-8
detail.hit.zdb_id:
2089076-X
