In:
ECS Transactions, The Electrochemical Society, Vol. 54, No. 1 ( 2013-06-28), p. 39-54
Abstract:
MOSFETs using III-V and Ge channels with low effective mass have been regarded as strongly important for high performance and low power CMOS under sub 10 nm regime. Key device technologies to realize the III-V/Ge MOSFETs on Si are addressed in this paper. We have recently realized HfO 2 /Al 2 O 3 gate stacks with EOT of 1 nm or less for both InGaAs and Ge, allowing us to simultaneously satisfy both thin EOT and good MOS interface properties as the common gate stacks. Record high mobility Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated by using HfO 2 /Al 2 O 3 /GeO x /Ge gate stacks. Also, self-align Ni-InGaAs is used as the metal S/D regions with low resistance, which are mandatory for shor-channel MOSFETs. We have realized 55-nm-L g InGaAs-OI MOSFETs with Ni-InGaAs S/D on Si substrates by employing direct wafer bonding between InGaAs and Si substrates with ultrathin Al 2 O 3 buried oxides. Also, by utilizing these technologies, we have demonstrated successful integration of InGaAs-OI nMOSFETs and Ge p-MOSFETs with superior device performance.
Type of Medium:
Online Resource
ISSN:
1938-5862
,
1938-6737
DOI:
10.1149/05401.0039ecst
Language:
Unknown
Publisher:
The Electrochemical Society
Publication Date:
2013
