In:
ECS Transactions, The Electrochemical Society, Vol. 58, No. 9 ( 2013-08-31), p. 137-148
Abstract:
CMOS utilizing high mobility III-V/Ge channels on Si substrates is expected to be one of promising devices for high performance and low power advanced LSIs in the future, because of the enhanced carrier transport properties. However, the device/process/ integration technologies of Ge/III-V n- and pMOSFETs for satisfying requirements of future node MOSFETs have not been established yet. In this paper, we address gate stack and channel engineering for enhancing the MOSFET performance with emphasis on thin EOT and ultrathin body, which are mandatory in the future nodes. As for Ge MOSFETs, GeO x /Ge interfaces formed by plasma post oxidation are shown to realize thin EOT, low D it and high mobility. By using these HfO 2 /Al 2 O 3 /GeO x /Ge gate stacks, Ge n- and p-MOSFETs with EOT of 0. 76 nm have been demonstrated with high electron (690 cm 2 /Vs) and hole (550 cm 2 /Vs) mobility. As for III-V MOSFETs, ultrathin InAs channels with MOS interface buffer layers are shown to provide high electron mobility under InAs thickness of 3 nm By utilizing this channel engineering, 55 nm-L ch quantum well channel InAs-OI n-MOSFETs have been demonstrated with superior short channel effect immunity and fairly high on current.
Type of Medium:
Online Resource
ISSN:
1938-5862
,
1938-6737
DOI:
10.1149/05809.0137ecst
Language:
Unknown
Publisher:
The Electrochemical Society
Publication Date:
2013
