In:
ECS Transactions, The Electrochemical Society, Vol. 35, No. 3 ( 2011-04-25), p. 33-53
Abstract:
Although limits of down-scaling of Si-CMOS FETs have been argued for many years, the down-scaling is the most realistic and effective way for the moment to decrease power consumption, increase performance, and also decrease the cost for massproduced integrated circuits, and thus, the CMOS down-scaling competition has heated-up among major semiconductor companies and their alliances. Because of its nature of effectively suppressing the off leakage current with gate around configuration, the Si nanowire FET has been thought be the ultimate structure for ultrasmall CMOS devices towards their downsizing limit. Recently, several experimental data of Si nanowire FETs with very high oncurrent much larger than that of planar MOSFETs have been published. Thus, Si nanowire FETs are now drawing attention as the most promising candidate for the mainstream CMOS devices in 2020s. In this paper, recent research status of Si nanowire FETs in experimental and theoretical works are described.
Type of Medium:
Online Resource
ISSN:
1938-5862
,
1938-6737
Language:
Unknown
Publisher:
The Electrochemical Society
Publication Date:
2011
