In:
Japanese Journal of Applied Physics, IOP Publishing, Vol. 61, No. SC ( 2022-05-01), p. SC1083-
Kurzfassung:
A nonvolatile lookup table (NV-LUT) circuit, which is a key component of a field-programmable gate array, is proposed for an energy-efficient yet high-performance binarized convolutional neural network (BCNN) accelerator. Since the active load is distributed to each configuration memory cell, the effect of the parasitic components is greatly reduced. Moreover, the use of a wired-OR logic-circuit style makes it possible to perform a high-speed logic operation. The proposed 6-input NV-LUT circuit using an active-load-localized single-ended circuit style is designed using a 45 nm CMOS technology and the delay is reduced by 30% with only 13% of hardware overhead compared to those of a conventional NV-LUT circuit. It is also demonstrated that the proposed NV-LUT circuit exhibits variation resilience against three process corners. The use of the proposed NV-LUT circuit also makes it possible to reduce 47% of the energy consumption of a BCNN accelerator for digit recognition compared to that of a conventional SRAM-LUT-based implementation.
Materialart:
Online-Ressource
ISSN:
0021-4922
,
1347-4065
DOI:
10.35848/1347-4065/ac51bf
Sprache:
Unbekannt
Verlag:
IOP Publishing
Publikationsdatum:
2022
ZDB Id:
218223-3
ZDB Id:
797294-5
ZDB Id:
2006801-3
ZDB Id:
797295-7
