In:
Materials Science Forum, Trans Tech Publications, Ltd., Vol. 600-603 ( 2008-9), p. 1147-1150
Abstract:
Threshold voltage (Vth) was measured on 4H-SiC power DMOSFET devices as a function
of temperature, gate stress, and gate stress time. Vth varied linearly with gate stress and gate stress time and inversely with temperature. This instability is explained with the trapping rate of channel
electrons at or near the SiO2-SiC interface. Since the measurement scale of Vth is large in this case (it takes approx. 20 s to measure Vth), it is assumed that fast interface traps, i.e., ones closer to the
interface, are already filled and do not contribute to the shift in Vth. Comparison with theoretical calculations shows the rate of carrier detrapping becomes higher with temperature and as a result the
measured value of Vth approaches the theoretical value.
Type of Medium:
Online Resource
ISSN:
1662-9752
DOI:
10.4028/www.scientific.net/MSF.600-603
DOI:
10.4028/www.scientific.net/MSF.600-603.1147
Language:
Unknown
Publisher:
Trans Tech Publications, Ltd.
Publication Date:
2008
detail.hit.zdb_id:
2047372-2