UID:
almahu_9948342718002882
Format:
1 online resource (various pagings) :
,
illustrations (some color).
ISBN:
9780750317320
,
9780750317313
Series Statement:
IOP ebooks. [2020 collection]
Content:
Pipelined architecture analog-to-digital converters (ADCs) have become the architecture of choice for high speed and moderate to high resolution devices. Subsequently, different techniques of the fault diagnosis by built in self-test (BIST) system have been developed. This book gives a rigorous, theoretical and mathematical analysis for the design of pipelined ADCs, along with detailed practical aspects of implementing it in very large-scale integration (VLSI). In each chapter a unique fault diagnosis technique for pipelined ADC has been proposed. Chapter 1 discusses a 1.8V 10-bit 500 mega samples-per-second parallel pipelined ADC, describing the design of high speed, low power, low voltage ADC in CMOS technology. Chapter 2 introduces a BIST system where both the circuit and its diagnosis tool are implemented on the same chip. Chapter 3 examines the design of an oscillation-based BIST system for a 1.8V 8-bit 125-mega samples per second pipelined ADC. Chapter 4 focuses on the evaluation of dynamic parameters of a pipelined ADC with an oscillation-based BIST. Chapter 5 covers reconfigurable BIST architecture for pipelined ADCs. The book is an ideal reference for graduate students and researchers within electrical, electronics and computer engineering.
Note:
"Version: 20200301"--Title page verso.
,
1. A 1.8 V, 10 bit, 500 mega samples per second parallel pipelined analog-to-digital converter -- 1.1. Introduction -- 1.2. Pipelined analog-to-digital converter architecture -- 1.3. Operational transconductance amplifier (OTA) -- 1.4. Sample-and-hold amplifier -- 1.5. Multiplying digital-to-analog converter (MDAC) -- 1.6. Comparator -- 1.7. Conclusion
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2. A. built-in self-test for a 1.8 V, 8 bit, 125 mega samples per second pipelined analog-to-digital converter -- 2.1. Organization of the chapter -- 2.2. Specifications of the pipelined ADC -- 2.3. Motivation and aims -- 2.4. Pipelined ADC architecture -- 2.5. A MATLAB model of the pipelined ADC -- 2.6. Results obtained in the Cadence environment -- 2.7. Built-in self-test (BIST) system -- 2.8. Simulation of the pipelined ADC -- 2.9. Future work
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3. Design of an oscillation-based built-in self-test system for a 1.8 V, 8 bit, 125 mega samples per second pipelined analog-to-digital converter -- 3.1. Introduction -- 3.2. Oscillation-based BIST principles -- 3.3. Implementation of oscillation-based BIST -- 3.4. Introduction to ADC dynamic testing -- 3.5. Conclusion
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4. An oscillation-based built-in self-test (BIST) system for dynamic performance parameter evaluation of an 8 bit, 100 MSPS pipelined ADC -- 4.1. Introduction -- 4.2. Oscillation-based BIST principles -- 4.3. Test stimulus generation -- 4.4. OTA-C filter -- 4.5. Dynamic parameter evaluation of a pipelined ADC -- 4.6. Fault analysis using the BIST system -- 4.7. Preparation of the layout and post-layout simulations -- 4.8. Conclusion
,
5. A reconfigurable built-in self-test architecture for a pipelined ADC -- 5.1. Introduction -- 5.2. The pipelined ADC -- 5.3. Oscillation-based built-in self-test system -- 5.4. Implementation of the ADC and OBIST -- 5.5. Conclusion.
,
Also available in print.
,
Mode of access: World Wide Web.
,
System requirements: Adobe Acrobat Reader, EPUB reader, or Kindle reader.
Additional Edition:
Print version: ISBN 9780750317306
Additional Edition:
ISBN 9780750317689
Language:
English
DOI:
10.1088/978-0-7503-1732-0
URL:
https://iopscience.iop.org/book/978-0-7503-1732-0
URL:
URL des Erstveröffentlichers
