Umfang:
1 Online-Ressource (311 Seiten)
Ausgabe:
1st ed
ISBN:
9783031253195
Serie:
Lecture Notes in Computer Science Series v.13820
Anmerkung:
Description based on publisher supplied metadata and other sources
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Intro -- Preface -- Organization -- Contents -- Physical Attacks -- Time's a Thief of Memory -- 1 Introduction -- 1.1 Can Tenants Covertly Communicate in ARM TrustZone? -- 1.2 Limitations of Related Prior Works -- 1.3 Attack Target and Our Contributions -- 1.4 Paper Organization -- 2 Background -- 2.1 OP-TEE Implementation -- 2.2 How ARM TrustZone Isolates Tenants -- 3 Attack Model -- 3.1 Covert Channel Assumptions -- 3.2 Attack Methodology Design Motivations -- 4 TA-to-CA Covert Communication -- 4.1 Data Collection/Target Profiling Phase -- 4.2 Attack Phase -- 4.3 Trade-Off Between Covert Channel Bandwidth and SNR -- 5 CA-to-TA Covert Communication -- 5.1 Setup -- 5.2 Measurements and Information Retrieval -- 6 Experimental Results -- 7 Countermeasures -- 8 Conclusion -- References -- Combined Fault Injection and Real-Time Side-Channel Analysis for Android Secure-Boot Bypassing -- 1 Introduction -- 2 Related Works -- 2.1 Bootloader Attacks -- 2.2 Attack Synchronization Issue -- 2.3 Existing Synchronization Methods -- 3 Frequency Detector -- 3.1 Frequency Detection Methodology -- 3.2 Frequency Detector Design -- 3.3 Frequency Detector Performances -- 4 Attack Environment Setup -- 4.1 Electromagnetic Fault Injection -- 4.2 Electromagnetic Leakage Measurement -- 4.3 Secure-Boot Vulnerability -- 4.4 Characteristic Frequency Research -- 5 Linux Kernel Authentication Bypassing on Android Secure-Boot -- 5.1 Experimental Setup -- 5.2 Experimental Results -- 6 Discussion -- 7 Conclusion -- References -- A Practical Introduction to Side-Channel Extraction of Deep Neural Network Parameters -- 1 Introduction -- 2 Background -- 2.1 Neural Networks -- 2.2 IEEE-754 Standard for Floating-Point Arithmetic -- 3 Related Work -- 3.1 API-Based Attacks -- 3.2 Timing Analysis -- 3.3 SCA-Based Extractions -- 4 Scope and Contributions -- 5 Experimental Setup
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5.1 Target Device and Setup -- 5.2 Inference Program -- 6 Threat Model -- 7 Challenges and Overall Methodology -- 7.1 Critical Challenges Related to SCA-Based Parameter Extraction -- 7.2 Our Methodology -- 8 Extraction Method and Experiments -- 8.1 Targeting Multiplication Operation -- 8.2 Extracting Parameters of a Perceptron -- 8.3 Targeting the Sign -- 8.4 Targeting One Layer -- 8.5 Targeting Few Layers -- 9 Future Works -- 9.1 What About Neuron Bias? -- 9.2 Targeting State-of-the-Art Functional Models -- 10 Conclusion -- References -- Physical Countermeasures -- A Nearly Tight Proof of Duc et al.'s Conjectured Security Bound for Masked Implementations -- 1 Introduction -- 2 Background -- 2.1 Problem Statement -- 2.2 Quantifying the Distance to Uniform -- 3 Nearly Tight Bounds -- 3.1 Upper Bounding the Mutual Information -- 3.2 From a MI Upper Bound to a Security Lower Bound -- 4 Conclusions -- A Side-Effect: Improving TCC 2016's Bounds -- References -- Short-Iteration Constant-Time GCD and Modular Inversion -- 1 Introduction -- 2 Related Work -- 2.1 BEA and BEEA -- 2.2 SCA of BEA and BEEA -- 2.3 CT-GCD and CTMI Algorithms -- 3 Short-Iteration CT-GCD and CTMI -- 3.1 Our Iteration Formula -- 3.2 The Number of Iterations -- 3.3 SICT-GCD and SICT-MI -- 4 Experiments Analysis -- 5 Conclusion -- References -- Protecting AES -- Guarding the First Order: The Rise of AES Maskings -- 1 Introduction -- 2 Preliminaries -- 2.1 Notation -- 2.2 Description of AES -- 2.3 The Threshold Glitch-Extended Probing Model -- 2.4 Boolean Masking and Threshold Implementations -- 3 Changing of the Guards with Randomness -- 4 Maskings of the S-Box -- 4.1 Overarching Components -- 4.2 Design I: Two-Share S-Box -- 4.3 Design II: Three-Share S-Box -- 4.4 Design III: Three-Share S-Box -- 5 Architecture -- 6 First-Order Probing Security
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7 Implementations and Physical Evaluations -- 7.1 Implementations and Comparison to Related Work -- 7.2 Evaluation -- 8 Conclusion -- References -- Rivain-Prouff on Steroids: Faster and Stronger Masking of the AES -- 1 Introduction -- 2 Preliminaries -- 2.1 Provably-Secure Masking of the AES -- 2.2 Formal Security Notions -- 3 Low-Level Field Arithmetic -- 3.1 Table-Based Multiplication -- 3.2 Basic First-Order Gadgets -- 4 New Exponentiation-Based Inversion -- 5 Masked AES -- 5.1 Round Transformations -- 5.2 Results and Comparison -- 6 Conclusions -- A Practical Leakage Assessment -- References -- Self-timed Masking: Implementing Masked S-Boxes Without Registers -- 1 Introduction -- 2 Background -- 2.1 Notations -- 2.2 The Domain-Oriented Masking -- 2.3 The Dual-Rail Encoding -- 2.4 Data Synchronization with the Muller C-Elements -- 3 Self-timed Masking Implementation -- 4 Implementation Results -- 5 Side-Channel Analysis -- 5.1 AES S-box Analysis -- 5.2 Full Design Analysis -- 5.3 Bivariate Analysis -- 6 Conclusion -- References -- Evaluation Methodologies -- An Evaluation Procedure for Comparing Clock Jitter Measurement Methods -- 1 Introduction -- 2 Modeling the Jitter Measurement Methods -- 2.1 Principle -- 2.2 Model Assumptions -- 2.3 Simulations Based on the Model and Their Precision -- 2.4 Hardware Constraints and Data Acquisition -- 3 Application of the New Methodology -- 3.1 Counter Method -- 3.2 Coherent Sampling Method -- 3.3 Differential Delay Line Method -- 3.4 Method Testing the Autocorrelation of Distant Samples -- 4 General Discussion -- 5 Conclusions -- References -- Comparing Key Rank Estimation Methods -- 1 Introduction -- 1.1 The Challenge in Practice -- 1.2 Recent Conceptual Advances -- 1.3 Assumptions, Gaps in Knowledge, and Our Contribution -- 2 Classical Key Rank Estimation vs. GEEA.
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2.1 Evaluating a Modern Algorithmic Ranking Algorithm -- 2.2 Evaluating GEEA Performance Characteristics -- 3 Challenging Synthetic Data Based Key Ranks -- 3.1 Theoretical Differences Between Approaches -- 3.2 Practical Differences Between Approaches: Correlation -- 3.3 Practical Differences Between Approaches: Gaussian Templates -- 4 Real Trace Experiments -- 5 Conclusion -- References -- Cycle-Accurate Power Side-Channel Analysis Using the ChipWhisperer: A Case Study on Gaussian Sampling -- 1 Introduction -- 2 Preliminaries -- 3 Measurement Setup -- 3.1 Target: STM32F4 -- 3.2 Trace: ChipWhisperer -- 3.3 Analyze: Overlaying the Trace with Corresponding Assembly Code -- 4 ChipWhisperer Firmware -- 5 '3́9'42'"̇613A''45'47'"603ASign-Flip Analysis -- 5.1 Power Analysis of Different Implementations -- 5.2 Analyzing Various New Versions -- 5.3 Two-Sided CDT Gaussian Sampler -- 6 Conclusion -- References -- Attacking NTRU -- Reveal the Invisible Secret: Chosen-Ciphertext Side-Channel Attacks on NTRU -- 1 Introduction -- 1.1 Related Work -- 1.2 Contributions -- 1.3 Organization -- 2 Preliminaries -- 2.1 Notation -- 2.2 NTRU in NIST PQC Round 3 -- 2.3 Threat Model -- 3 SPA on NTRU Reference Implementation -- 3.1 A Preliminary Idea -- 3.2 Attack 1: Recovering Differences Between Adjacent Coefficients -- 3.3 Attack 2: Recovery of the ''Invisible'' Secret Polynomial -- 4 Applicability to pqm4 -- 4.1 Direct Recovery of f -- 4.2 Recovery via g -- 5 Conclusion -- References -- Security Assessment of NTRU Against Non-Profiled SCA -- 1 Introduction -- 2 NTRU Description and Implemented Countermeasures -- 2.1 NTRU Algorithm and Notations -- 2.2 Targeted Algorithmic Setting and Operation -- 2.3 Countermeasures -- 3 Side-Channel Analysis -- 3.1 Target -- 3.2 Setup and Pre-processing -- 3.3 Defeating the Rotation Countermeasure
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3.4 Last Phase of the Attack: Discriminating Between 0 and 1 -- 3.5 Summary of Attack and Results -- 4 Conclusion -- References -- Next-Generation Cryptography -- Post-Quantum Protocols for Banking Applications -- 1 Introduction -- 2 Existing Protocols -- 2.1 EMV CDA Protocol -- 2.2 BDH-Based Protocol -- 3 Post-Quantum and Hybrid Versions -- 3.1 PQ Version of EMV CDA Protocol -- 3.2 PQ Version of BDH-Based Protocol -- 3.3 Hybrid Versions -- 4 Practical Implementation -- 4.1 Post-quantum Algorithms Selection -- 4.2 Implementation Description -- 4.3 Performances Analysis -- 5 Conclusion -- References -- Analyzing the Leakage Resistance of the NIST's Lightweight Crypto Competition's Finalists -- 1 Introduction -- 2 Mode-level Analysis -- 3 Hardware Implementations -- 3.1 Masked Implementation of the Primitives -- 3.2 Implementation of the Modes -- 4 Conclusion -- References -- Author Index
Weitere Ausg.:
Erscheint auch als Druck-Ausgabe Buhan, Ileana Smart Card Research and Advanced Applications Cham : Springer International Publishing AG,c2023 ISBN 9783031253188
Sprache:
Englisch
Schlagwort(e):
Konferenzschrift
