Format:
1 Online-Ressource (viii, 145 Seiten)
Edition:
1st ed
Edition:
Electronic reproduction Available via World Wide Web
ISBN:
1598291238
,
9781598291230
Series Statement:
Synthesis lectures in computer architecture #3
Content:
Includes bibliographical references
Content:
Chip multiprocessors - also called multi-core microprocessors or CMPs for short - are now the only way to build high-performance microprocessors, for a variety of reasons. Large uniprocessors are no longer scaling in performance, because it is only possible to extract a limited amount of parallelism from a typical instruction stream using conventional superscalar instruction issue techniques. In addition, one cannot simply ratchet up the clock speed on today's processors, or the power dissipation will become prohibitive in all but water-cooled systems. Compounding these problems is the simple fact that with the immense numbers of transistors available on today's microprocessor chips, it is too costly to design and debug ever-larger processors every year or two
Content:
The case for CMPs -- Improving throughput -- Improving latency automatically -- Improving latency using manual parallel programming -- A multicore world: The future of CMPs
Note:
Description based upon print version of record
,
The Case for CMPs; A NEW APPROACH: THE CHIP MULTIPROCESSOR (CMP); The Application Parallelism Landscape; A Simple Example: Superscalar vs. CMP; Simulation Results; This Book: Beyond Basic CMPs; Improving Throughput; SIMPLE CORES AND SERVER APPLICATIONS; The Need for Multithreading within Processors; Maximizing the Number of Cores on the Die; Providing Sufficient Cache and Memory Bandwidth; CASE STUDIES OF THROUGHPUT-ORIENTED CMPs; Example 1: The Piranha Server CMP; Example 2: The Niagara Server CMP; Example 3: The Niagara 2 Server CMP; Simple Core Limitations; GENERAL SERVER CMP ANALYSIS
,
Simulating a Large Design SpaceChoosing Design Datapoints; Results; Discussion; Improving Latency Automatically; PSEUDO-PARALLELIZATION: ``HELPER'' THREADS; AUTOMATED PARALLELIZATION USING THREAD-LEVEL SPECULATION (TLS); AN EXAMPLE TLS SYSTEM: HYDRA; The Base Hydra Design; Adding TLS to Hydra; Using Feedback from Violation Statistics; Performance Analysis; Completely Automated TLS Support: The JRPM System; Concluding Thoughts on Automated Parallelization; Improving Latency Using Manual Parallel Programming; USING TLS SUPPORT AS TRANSACTIONAL MEMORY
,
An Example: Parallelizing Heapsort Using TLSParallelizing SPEC2000 with TLS; TRANSACTIONAL COHERENCE AND CONSISTENCY (TCC): MORE GENERALIZED TRANSACTIONAL MEMORY; TCC HARDWARE; TCC Software; TCC Performance; MIXING TRANSACTIONAL MEMORY AND CONVENTIONAL SHARED MEMORY; A Multicore World: The Future of CMPs
,
Electronic reproduction Available via World Wide Web
,
Mode of access: World Wide Web.
,
System requirements: Adobe Acrobat Reader.
Additional Edition:
ISBN 159829122X
Additional Edition:
ISBN 9781598291223
Additional Edition:
Erscheint auch als Druck-Ausgabe Chip Multiprocessor Architecture Techniques to Improve Throughput and Latency
Language:
English
Keywords:
Electronic books
DOI:
10.2200/S00093ED1V01Y200707CAC003
