Format:
1 Online-Ressource (320 pages)
ISBN:
0818671076
,
9780818671074
Content:
An invited talk recounts Intel's experience with increasing die yield through CAD algorithms, and a panel discussion examines tools for the extracting of critical areas for a yield analysis of VLSI design. Others of the 34 papers cover critical area analysis, defect sensitivity and reliability, fault tolerant architectures and arrays, yield projection and enhancement, fault tolerant and testing techniques, and self-checking and coding techniques. No subject index. Annotation copyright by Book News, Inc., Portland, OR
Language:
English
Keywords:
Konferenzschrift
