Ihre E-Mail wurde erfolgreich gesendet. Bitte prüfen Sie Ihren Maileingang.

Leider ist ein Fehler beim E-Mail-Versand aufgetreten. Bitte versuchen Sie es erneut.

Vorgang fortführen?

Exportieren
  • 1
    Online-Ressource
    Online-Ressource
    Berlin, Heidelberg :Springer Berlin Heidelberg,
    UID:
    almahu_9947920522402882
    Umfang: XVI, 196 p. , online resource.
    ISBN: 9783540246572
    Serie: Lecture Notes in Computer Science, 2963
    Inhalt: In the mid 1960s, when a single chip contained an average of 50 transistors, Gordon Moore observed that integrated circuits were doubling in complexity every year. In an in?uential article published by Electronics Magazine in 1965, Moore predicted that this trend would continue for the next 10 years. Despite being criticized for its “unrealistic optimism,” Moore’s prediction has remained valid for far longer than even he imagined: today, chips built using state-- the-art techniques typically contain several million transistors. The advances in fabrication technology that have supported Moore’s law for four decades have fuelled the computer revolution. However,this exponential increase in transistor density poses new design challenges to engineers and computer scientists alike. New techniques for managing complexity must be developed if circuits are to take full advantage of the vast numbers of transistors available. In this monograph we investigate both (i) the design of high-level languages for hardware description, and (ii) techniques involved in translating these hi- level languages to silicon. We propose SAFL, a ?rst-order functional language designedspeci?callyforbehavioralhardwaredescription,anddescribetheimp- mentation of its associated silicon compiler. We show that the high-level pr- erties of SAFL allow one to exploit program analyses and optimizations that are not employed in existing synthesis systems. Furthermore, since SAFL fully abstracts the low-leveldetails of the implementation technology, we show how it can be compiled to a range of di?erent design styles including fully synchronous design and globally asynchronous locally synchronous (GALS) circuits.
    Anmerkung: 1. Introduction -- 1. Introduction -- 2. Related Work -- 3. The SAFL Language -- 4. Soft Scheduling -- 5. High-Level Synthesis of SAFL -- 6. Analysis and Optimisation of Intermediate Code -- 7. Dealing with I/O -- 8. Combining Behaviour and Structure -- 9. Transformation of SAFL Specifications -- 10. Case Study -- 11. Conclusions and Further Work.
    In: Springer eBooks
    Weitere Ausg.: Printed edition: ISBN 9783540213062
    Sprache: Englisch
    Fachgebiete: Informatik
    RVK:
    URL: Volltext  (lizenzpflichtig)
    Bibliothek Standort Signatur Band/Heft/Jahr Verfügbarkeit
    BibTip Andere fanden auch interessant ...
Schließen ⊗
Diese Webseite nutzt Cookies und das Analyse-Tool Matomo. Weitere Informationen finden Sie auf den KOBV Seiten zum Datenschutz