In:
ECS Transactions, The Electrochemical Society, Vol. 14, No. 1 ( 2008-08-22), p. 203-211
Abstract:
CMOS device/circuit performance involving mobility-enhanced strain-engineering in the channel region is studied via process and device simulations. It is shown that strained-Si (SS) devices could be applied for low-power design by lowering supply voltage. A physics-based stress induced mobility model has been developed and implemented in Synopsys Sentaurus Device simulator. The trade-offs for power and performance in strained-Si devices and circuits are discussed.
Type of Medium:
Online Resource
ISSN:
1938-5862
,
1938-6737
Language:
Unknown
Publisher:
The Electrochemical Society
Publication Date:
2008
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